Abstract
It is well known that timing jitter can degrade the bit error rate of receivers that recover the clock from input data. However, timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are required in repeaterless low swing on-chip interconnects. We first discuss how timing jitter can result in a large increase in the settling time of the clock recovery circuit. Next, the circuit is modelled as a Markov chain with absorbing states. The mean time to absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated through behavioural simulations of the circuit, the results of which match well with the model predictions. We consider circuits with (1) data dependent jitter, (2) random jitter, and (3) combination of both of them. We show that a mismatch between the strengths of up and down corrections of the retiming can reduce the settling time. In particular, a 10% mismatch can reduce the mean settling time by up to 40%. We leverage this fact toward improving the settling time performance, and propose useful techniques based on biased training sequences and mismatched charge pumps. We also present a coarse+fine clock retiming circuit, which can operate in coarse first mode, to reduce the settling time substantially. These fast settling retiming circuits are verified with circuit simulations.
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Appendices
Appendices
Appendix A: Derivation of the deterministic component of the settling time
For mesochronous systems, a clock running at the correct frequency is available and only the phase has to be corrected. Hence, the clock recovery circuit can be of the first order, i.e., the loop filter is a single capacitor [5, 8]. When a bang-bang phase detector is used, the capacitor voltage (\(V_c\)) is quantized to a step size given by
Here \(K_{CP}\) is the gain of the charge pump, expressed in terms of the charge pump current \(I_{CP}\) and the clock period T. Hence, the step size of the phase corrections is
The number of phase correction steps (M) needed for achieving lock can be written as
The settling time can then be written as
where \(\alpha\) is the data activity factor. From (2), (3) and (4), the settling time expression in (1) follows.
Appendix B: Mean time to absorption of a Markov chain
Knowing the probability transition matrix of a Markov chain, the mean time to absorption and its variance can be computed. We will outline an example computation in this “Appendix”. The state diagram of the Markov chain representation of the clock recovery circuit, for data with 1 bit ISI, is shown in Fig. 17. The states corresponding to \(-T_{\mathcal {W}}/2\) and \(T_{\mathcal {W}}/2\), which are at the edges of the window of susceptibility, are absorbing states. The probability transition matrix \(\bar{P}\) for this Markov chain can be written as
To calculate the mean time to absorption (and the variance of the time to absorption), \(\bar{P}\) is first written in the canonical form [24]. This is obtained by reordering the entries in \(\bar{P}\) to separately aggregate all the transient and absorbing states respectively. Hence, \(\bar{P}\) can be written as
Here Q is a square matrix which captures the transitions from one transient state to another transient state, R captures the transitions from transient states to absorbing states and I is an identity matrix. The fundamental matrix N can be computed using the equation
where \(\tilde{I}\) is an identity matrix of the same dimensions as Q. Conditioned on the starting position, the mean time to absorption (\(T_{mean}\)), in terms of the number of steps, is given by
where \(C^1\) is a column vector with number of rows equal to the number of transient states, and with all entries as 1. The variance of the time to absorption (in terms of number of steps), conditioned on the starting position, is calculated as
Here \(T_{mean}^{sq}\) is obtained by squaring the elements of \(T_{mean}\).
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Kadayinti, N., Budkuley, A.J., Baghini, M.S. et al. Effect of jitter on the settling time of mesochronous clock retiming circuits. Analog Integr Circ Sig Process 101, 623–640 (2019). https://doi.org/10.1007/s10470-018-1344-9
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DOI: https://doi.org/10.1007/s10470-018-1344-9