Abstract
Quantum-dot cellular automata (QCA) has emerged as a crucial alternative to CMOS technology in the recent years. However, the main hindrance in advancement of QCA technology is that it suffers from various types of manufacturing defects and variations. Several cell misplacement defects introduced in the deposition phase of manufacturing process of QCA have been found to be frequent. Manifestation of such defects may greatly impact the functionality and performance of QCA circuits. A few designs of various QCA modules based on some ad-hoc tricks have shown to diminish the negative effect of defects significantly, thereby making the design fault(defect)-tolerant. However, in the absence of proper insights, they fail to provide any guideline towards fault-tolerant design of QCA circuits in general. Moreover, these designs mostly compromise a lot with the other important design parameters such as area, latency. In this paper, we propose a set of comprehensive guidelines that will elucidate the path for systematic design of practical fault-tolerant circuits in QCA. The guidelines have been derived based on some critical observations made during extensive simulation experiments carried out in QCADesigner followed by theoretical explanation. The usage of the proposed guidelines has been illustrated by designing an adder circuit.
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References
Angizi, S., et al. (2014). Novel robust single layer wire crossing approach for exclusive or sum of products logic design with quantum-dot cellular automata. Journal of Low Power Electronics, 10, 259–271.
Breitkreutz, S., et al. (2013). Experimental demonstration of a 1-bit full adder in perpendicular nanomagnetic logic. IEEE Transactions on Magnetics, 49, 4464–4467.
Campos, C. A. T., et al. (2016). Use: A universal, scalable, and efficient clocking scheme for QCA. IEEE Transactions on Computer-Aided Design of Integreted Circuits and Systems, 35, 513–517.
Chen, T. C. (2006). Overcoming research challenges for CMOS scaling: Industry directions. In Proceedings of 8th international conference on solid-state and integrated circuit technology (ICSICT) (pp. 4–7)
Cho, H., & Swartzlander, E. E. (2009). Adder and multiplier design in quantum-dot cellular automata. IEEE Transactions on Computers, 58(6), 721–727.
Cowburn, R. P., & Welland, M. E. (2000). Room temperature magnetic quantum cellular automata. Science, 287, 1466–1468.
Farazkish, R. (2014). A new quantum-dot cellular automata fault-tolerant five-input majority gate. Journal of Nanoparticle Research, 16, 1–7.
Farazkish, R., & Khodaparast, F. (2015). Design and characterization of a new fault-tolerant full-adder for quantum-dot cellular automata. Microprocessors and Microsystems, 39, 426–433.
Fijany, A., & Toomarian, B. N. (2001). New design for quantum dots cellular automata to obtain fault tolerant logic gates. Journal of Nanoparticle Research, 3, 27–37.
Hanninen, I., & Takala, J. (2007). Robust adders based on quantum-dot cellular automata. In IEEE international conference on application-specific systems, architectures and processors (pp. 391–396)
Huang, J., et al. (2006). Defect tolerance of QCA tiles. In Design, Automation and Test in Europe (Vol. 1, pp. 1–6)
Kim, K., et al. (2005) Towards designing robust QCA architectures in the presence of sneak noise paths. In Proceedings of the design, automation and test in Europe conference and exhibition (DATE) (Vol. 2, pp. 1214–1219)
Kumar, D., & Mitra, D. (2016). Design of a practical fault-tolerant adder in QCA. Microelectronics Journal, 53, 90–104.
Lent, C. S., & Tougaw, P. D. (1997) A device architecture for computing with quantum dots. In Proceedings of the IEEE (Vol. 85, pp. 541–557)
Lent, C. S., et al. (1993). Quantum cellular automata. Nanotechnology, 4, 49–57.
Lent, C. S., et al. (1994). Quantum cellular automata: the physics of computing with arrays of quantum dot molecules. In Workshop on physics and computation (pp. 5–13)
Liu, W., et al. (2011) Design rules for quantum-dot cellular automata. In Proceedings of IEEE international symposium on circuits and systems (pp. 2361–2364)
Mardiris, V. A., & Karafyllidis, I. G. (2010). Design and simulation of modular 2n to 1 quantum-dot cellular automata (QCA) multiplexers. International Journal of Circuit theory and Applications, 38, 771–785.
Mitic, M., et al. (2006). Demonstration of a silicon-based quantum cellular automata cell. Applied Physics Letters, 89, 013503–013511.
Momenzadeh, M., et al. (2004). Quantum cellular automata: New defects and faults for new devices. In 18th international parallel and distributed processing symposium (pp. 207–214)
Momenzadeh, M., et al. (2005). Modeling QCA defects at molecular-level in combinational circuits. In International symposium on defect and fault tolerance in vlsi systems (pp. 208–216)
Niemier, M. T., et al. (2004). Using circuits and systems-level research to drive nanotechnology. In IEEE international conference on computer design (pp. 302–309)
Orlov, A. O., et al. (1997). Realization of a functional cell for quantum-dot cellular automata. Science, 277, 928–930.
Pudi, V., & Sridharan, K. (2012). Low complexity design of ripple carry and Brent-Kung adders in QCA. IEEE Transactions on Nanotechnology, 11(1), 105–119.
Pudi, V., & Sridharan, K. (2012). New decomposition theorems on majority logic for low-delay adder designs in quantum dot cellular automata. IEEE Transactions on Circuits and Systems-II: Express Briefs, 59, 678–682.
Roohi, A., et al. (2015). Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder. Microelectronics Journal, 46, 531–542.
Sen, B., et al. (2013). Design of efficient full adder in quantum-dot cellular automata. The Scientific World Journal, 2013, 1–10.
Sen, B., et al. (2014). Efficient design of fault tolerant tiles in QCA. In Annual IEEE India conference (INDICON) (pp. 1–6)
Tahoori, M. B., et al. (2004). Defects and faults in quantum cellular automata at nano scale. In Proceedings of the 22nd IEEE VLSI test symposium (pp. 291–296)
Tahoori, M. B., et al. (2004). Testing of quantum cellular automata. IEEE Transactions on Nanotechnology, 3(4), 432–442.
Tougaw, P. D., & Lent, C. S. (1994). Logical devices implemented using quantum cellular automata. Journal of Applied Physics, 75(3), 1818–1825.
Vankamamidi, V., et al. (2008). Two dimensional schemes for clocking/ timing of QCA circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 27, 34–44.
Walus, K., et al. (2004). QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata. IEEE Transactions on Nanotechnology, 3(1), 26–31.
Walus, K., et al. (2005). Simple 4-bit processor based on quantum-dot cellular automata (QCA). In Proceedings of the 16th international conference on application-specific systems, architecture and processors (ASAP) (pp. 1–6). Computer Society
Wang, W., et al. (2003). Quantum-dot cellular automata adders. In 3rd IEEE conference on nanotechnology (Vol. 1, pp. 461–464)
Zhang, R., et al. (2005). Performance comparison of quantum-dot cellular automata adders. In International symposium on circuits and systems (pp. 2522–2526)
Acknowledgements
The authors would like to thank Professor Bhargab B. Bhattacharya of Indian Statistical Institute, Kolkata and Dr. Bibhash Sen of NIT Durgapur for their valuable suggestions.
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Kumar, D., Mitra, D. A systematic approach towards fault-tolerant design of QCA circuits. Analog Integr Circ Sig Process 98, 501–515 (2019). https://doi.org/10.1007/s10470-018-1270-x
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DOI: https://doi.org/10.1007/s10470-018-1270-x