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Analog Integrated Circuits and Signal Processing

, Volume 97, Issue 2, pp 215–223 | Cite as

Experimental implementation of \(\Delta \Sigma \)AD modulator with dynamic analog components

  • Chunhui Pan
  • Hao San
Article

Abstract

This paper presents an experimental prototype of 2nd-order multi-bit \(\Delta \Sigma \)AD modulator with dynamic analog components for low power and high signal to noise and distortion (SNDR) application. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feed-forward modulator is realized by a passive-adder embedded successive approximation register analog to digital converter which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power at all when a pre-amplifier is not used. Proposed modulator is fabricated in TSMC 90 nm CMOS technology. Measurement results of the modulator dynamic range is over 84 dB. Measured peak SNDR = 77.51 dB, SNR = 80.08 dB are achieved for the bandwidth of BW = 94 kHz while a sinusoid differential \(-1\) dBFS input is sampled at 12 MS/s. The total analog power consumption of the modulator is 0.37 mW while the supply voltage is 1.1 V.

Keywords

Multi-bit \(\Delta \Sigma \) modulator Ring amplifier SAR ADC Switched-capacitor circuit 

Notes

Acknowledgements

This work was supported by JSPS Grant-in-Aid for Scientific Research (C) 25420345. This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc.

References

  1. 1.
    Elzakker, M., Tujil, E., Geraedts, P., Schinkel, D., Klumperink, E., & Nauta, B. (2008). A 1.9 μW 4.4 fJ/conversion-step 10 b 1 MS/s charge-redistribution ADC. In IEEE ISSCC 2008, digest of technical papers (pp. 244–610). doi: 10.1109/ISSCC.2008.4523148.Google Scholar
  2. 2.
    Schreier, R., & Temes, G. (2004). Understanding delta-sigma data converters. Hoboken: Wiley-IEEE Press.CrossRefGoogle Scholar
  3. 3.
    Silva, J., Moon, U., Steensgaard, J., & Temes, G. C. (2001). Wideband low-distortion delta-sigma ADC topology. Electronics Letters, 37(12), 737–738.  https://doi.org/10.1049/el:20010542.CrossRefGoogle Scholar
  4. 4.
    Pan, C., & San, H. (2015). A low-distortion delta-sigma modulator with ring amplifier and passive adder embedded SAR quantizer. In ISPACS2015 (pp. 299–302).  https://doi.org/10.1109/ISPACS.2015.7432784.
  5. 5.
    Pan, C., & San, H. (2016). A \(\Delta \Sigma \)AD modulator with SAR quantizer and ring amplifier. IEICE Transactions on Fundamentals (Japansese Edition), J99—-A(8), 262–269.Google Scholar
  6. 6.
    Hershberg, B., Weaver, S., Sobue, K., Takeuchi, S., Hamashita, K., & Moon, Un-Ku. (2012). Ring amplifiers for switched capacitor circuits. IEEE Journal of Solid State Circuits, 47(12), 2928–2942.  https://doi.org/10.1109/JSSC.2012.2217865.CrossRefGoogle Scholar
  7. 7.
    Lim, Y., & Flynn, M. (2014). A 100 MS/s, 10.5 Bit, 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers. In IEEE ISSCC 2014 digest of technical papers (pp. 202–203).  https://doi.org/10.1109/ISSCC.2014.6757400.
  8. 8.
    Lim, Y., & Flynn, M. (2015). A 1 mW 71.5 dB SNDR 50 MS/s 13 bit fully differential ring amplifier based SAR-assisted pipeline ADC. IEEE Journal of Solid-State Circuits, 50(12), 2901–2911.  https://doi.org/10.1109/JSSC.2015.2463094.CrossRefGoogle Scholar
  9. 9.
    Park, Y., Kwon, T., Cho, K., Kwak, Y., Ahn, G., Shin, C., Lee, M., You, S., & Park, H. (2012). A 1.1 V 82.3 dB audio \(\Delta \Sigma \) ADC using asynchronous SAR type quantizer. In 19th IEEE international conference on electronics, circuits and systems (ICECS 2012) (pp. 637–640).  https://doi.org/10.1109/ICECS.2012.6463555.
  10. 10.
    Chao, I., Hou, C., Liu, B., Chang, S., & Huang, C. (2014). A single opamp third-order low-distortion delta-sigma modulator with SAR quantizer embedded passive adder. IEICE Transactions on Electronics, E97–C(6), 526–537.  https://doi.org/10.1587/transele.E97.C.526.CrossRefGoogle Scholar
  11. 11.
    Kuo, T., Chen, K., & Yeng, H. (2002). A wideband CMOS sigma-delta modulator with incremental data weighted averaging. IEEE Journal of Solid-State Circuits, 37(1), 11–17.  https://doi.org/10.1109/4.974541.CrossRefGoogle Scholar
  12. 12.
    Bilhan, E., & Maloberti, F. (2009). A wideband sigma-delta modulator with cross-coupled two-paths. IEEE Transactions on Circuits and Systems I, 56(5), 886–893.MathSciNetCrossRefGoogle Scholar
  13. 13.
    Rajaee, O., Takeuchi, S., Aniya, M., Hamashita, K., & Moon, U. (2011). Low-OSR over-ranging hybrid ADC incorporating noise-shaped two-step quantizer. IEEE Journal of Solid-State Circuits, 46(11), 2458–2468.CrossRefGoogle Scholar
  14. 14.
    Abo, A. M., & Gray, P. R. (1999). A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. Journal of Solid-State Circuits, 34(5), 599–606.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Tokyo City UniversityTokyoJapan

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