A 14-bit 500-MS/s DAC with 211-MHz 70 dB SFDR bandwidth using TRI-DEMRZ

  • Longqiang Lai
  • Xueqing Li
  • Jianan Liu
  • Huazhong Yang


Time-relaxed interleaving dynamic element matching return-to-zero (TRI-DEMRZ) is proposed and verified in this paper to improve the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs). It incorporates time-relaxed interleaving (TRI), return-to-zero, and the dynamic-element-matching techniques, in a way that fosters the strength of each technique. As analyzed in this paper, merits beyond the combination of these techniques could be achieved. Firstly, TRI-DEMRZ provides a new dimension in the space domain, rather than the time domain, to explore the methods of mitigating nonlinear switching distortions. Secondly, this paper proves that, the image tone caused by typical channel mismatches between interleaved sub-DACs can be randomized into noise with TRI-DEMRZ. Circuit simulations and analysis are provided. An experimental 14-bit 500-MS/s current-steering DAC in 65 nm CMOS has been fabricated and measured, showing 81 dB SFDR at 5.5 MHz and more than 70 dB SFDR up to 211 MHz bandwidth. The SFDR improvement achieved by TRI-DEMRZ is more than 10 dB, which further verifies the effectiveness of TRI-DEMRZ.


Digital-to-analog converter (DAC) Dynamic element matching (DEM) Channel mismatch Time-relaxed interleaving Current-steering 

1 Introduction

While most high-speed digital-to-analog converters (DACs) are implemented in the current-steering topology because of the high intrinsic switching speed and moderate matching property, recent research has revealed two main bottlenecks towards a high dynamic range [1, 2, 3, 4]. One is the current source mismatch that affects the output amplitude. The other one is the nonlinear distortion caused by code-dependent switching glitches, which becomes more severe at a higher frequency with inevitable switching time mismatch and more switching activities.

Among various approaches, dynamic element matching (DEM) and return-to-zero (RZ) techniques are widely used to mitigate the aforementioned two aspects [1, 2, 4, 5]. With sufficient randomization, DEM is effective in averaging out current source mismatches. Meanwhile, RZ techniques are effective in mitigating the inter-symbol-interference (ISI) to reduce the code-dependent switching distortions. In [2], dynamic element matching return-to-zero (DMRZ) combined DEM and half-a-cycle RZ, leading to the first CMOS DAC with 70 dB SFDR up to 800 MHz.

Collectively incorporating the advantages of both the DMRZ technique in [2] and the time-relaxed interleaving technique in [3, 4, 6, 7], we have proposed TRI-DEMRZ, as depicted in Fig. 1. Compared with our previous effort in [4], this paper provides the first experimental measurement verifications and also fundamental analysis of TRI-DEMRZ that shows significant highlights, including:
Fig. 1

The concept of TRI-DEMRZ

  • The proposed TRI-DEMRZ reveals and confirms a new design dimension by trading space (associated area and power) for better dynamic performance with assisting digital signal processing techniques such as randomization. Note that, in our proposed TRI-DEMRZ, switching distortions in the final output are reduced by means of space domain randomization, which is fundamentally different from the previous DMRZ method that deals with switching distortions in the time domain, which will be analyzed in Sect. 2. Such a new dimension provides more chance of distortion suppression and performance enhancement.

  • The combination of interleaving and DEM, not only randomizes the static mismatch of current sources inside each sub-DAC, but also randomizes the channel mismatch between the two sub-DACs. In this paper, we theoretically prove that under certain mismatch distribution, the channel mismatch between interleaved sub-DACs can be randomized, and the related image tone can be smashed into noise with TRI-DEMRZ. In this way, TRI-DEMRZ provides a new method to deal with the channel mismatch in interleaving.

The rest of this paper is organized as follows. Section “Static mismatches and switching distortions” revisits the existing study of current source mismatches and code-dependent switching glitches revealing the new design dimension of TRI-DEMRZ. The derivation and analysis of channel mismatch randomization using TRI-DEMRZ are provided in Section “Channel mismatch randomization”. The implementation and measurement of the experimental DAC are provided in Section “Implementation and experiment”. Finally, Section “Conclusion” concludes this paper.

2 Static mismatches and switching distortions

This section revisits the inherent features of the current source mismatches and code-dependent switching glitches, so as to get in-depth understanding of the pros and cons of existing solutions. This also shows how DEM and RZ techniques could potentially outperform or collaborate with other techniques. Then the basic concept of TRI-DEMRZ technique is revisited to show how it expands the design space for a higher dynamic range.

2.1 Problems in dealing with inter sub-DACs current source mismatches

Various sources result in systematic and random mismatches between current sources in fabricated current-steering DACs. These mismatches not only limit the static output signal amplitude, but also deteriorate the spectral performance [1, 2, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]. DEM is a method to deal with the mismatches by selecting current sources dynamically from random places in the current source array to make the integrated amplitude errors less code-dependent [1, 2]. Such randomization leads to averaging of the mismatches, and also contributes to harmonic distortion suppression. As the effectiveness of existing DEM on the mismatch noise shaping depends on “averaging over time” [2, 20], signals with amplitude near full scale at a higher frequency have less room for randomization and consequently, less mismatch averaging benefits in wideband Nyquist DACs. Nevertheless, for applications where SFDR is the bottleneck due to the current source mismatches, DEM is intriguing to improve SFDR by turning distortions into flat noise [1].

Meanwhile, there is urgent need of a good method to deal with the channel mismatch between the sub-DACs. Such channel mismatches exist when an interleaving DAC has more than one sub-DACs, as in [3, 4]. Section 2.3 of this paper will introduce the proposed interleaving DEM method for such DACs.

2.2 Problems in dealing with switching glitch distortions

The performance of conventional high-speed current-steering DACs is sensitive to the code-dependent switching glitches that cause harmonic distortions at the output [1, 2, 3, 21, 22, 23, 24, 25, 26, 27, 28]. Figure 2 illustrates two such dominant distortion sources of (1) coupled switching glitches from the switch control signals directly to the current routes, and (2) charge variation in each current source due to output amplitude modulation or varying current delivered by the differential switches. With more frequent switching activities, these distortions become more severe at a higher frequency. It is noted that these effects relate to the previous and current input digital codes of the DAC, generating inter-symbol-interference (ISI) [28, 29]. To mitigate these effects, circuit and layout optimizations could be applied, such as transistor size and biasing tuning, switch control signal swing and cross-over voltage adjustment, layout parasitics reduction, and tree-like layout usage, etc. [2, 3, 25, 27]. Meanwhile, RZ techniques have also been proved useful [30, 31, 32]: Analog RZ (ARZ) with additional reset-and-track operations could isolate the output from code-dependent settling glitches and only tracks the settled deglitched signal, with the overhead of additional re-sampling circuitry with parasitics and limit the high-frequency performance [33, 34]; Digital RZ (DRZ) modifies only the digital decoder so that the analog output is reset after every code accordingly, showing effectiveness in removing the ISI effects [3, 30].
Fig. 2

Nonlinear switching glitches due to code-dependent gate coupling and charge resettling modulated by the output voltage during a switching transition [25]

Nevertheless, it is important to understand that even if the ISI effects (history effects) are removed, some harmonics induced by the input-code-dependent effects mentioned above could not be fully eliminated. For example, the switching or re-sampling timing skews [35], the re-sampling coupling glitches or switch coupling glitches, as well as the charge resettling at the internal nodes inside each current route due to switching or re-sampling, will cause code-dependent glitches with carry-on harmonics at the DAC output. Therefore, these approaches to a high dynamic range, either by optimizing the existing circuit, layout, segmentation, adding dummy switching activities, or employing RZ operations, are useful, but still have inherent limitations for a DAC with a high SFDR.

2.3 Proposed TRI-DEMRZ in comparison with DEM and interleaving techniques

Dynamic random switching techniques provide another effective way to suppress the harmonic distortions by using code-independent switching [1, 2, 3, 30, 36, 37, 38]. In the time domain, the random operation could incorporate with RZ so that random and non-random operations are carried out alternately in phases of half clock cycles [2, 3, 30]. The random operation could be either in the phase of RZ, as in digital random return-to-zero (DRRZ) and TRI-DRRZ [3, 30], or in the phase of normal operation, as in DMRZ [2]. Figure 3(a) illustrates the comparison between NRZ, DRRZ, and DMRZ output.
Fig. 3

a The output waveform comparison between NRZ, DRRZ, DMRZ and TRI-DRRZ, showing different settling behavior [3]. b The basic structure of TRI-DRRZ [3]

The problems of existing incorporated DEM and RZ methods, as revealed in [3], are high-speed design challenges or drawbacks, including (1) tight timing requirement as the switching activities need to settle within half a clock period, and (2) signal energy loss, and higher image tones in the 2nd Nyquist zone to filter out due to the RZ output pattern. The mitigating method is time-relaxed interleaving (TRI) [3], which uses two parallel interleaving sub-DACs, each operating in a mode of alternate NRZ and RZ that settles within one full clock period instead of half a clock period. Figure 3 shows the TRI-DRRZ waveforms. It is clear that the two DRRZ problems are solved. The SFDR can also be higher because the signal power is higher than DRRZ while the total number of switching activities remains the same.

The technique of TRI in [3] is a new concept to seek for higher performance by trading extra space or area while doing random switching, which is fundamentally different from the previous DRRZ or DMRZ method of doing it in the time domain. The performance improvement would be significant when timing and amplitude mismatches caused by the increased area are not yet the performance bottleneck. Unfortunately, the previously proposed technique of TRI-DRRZ in [3] did not make full use of TRI to deal with current source mismatches in each subDAC, or between subDACs. This is because subDACs in [3] are (1) physically and operationally independent of each other, and (2) thermometer-decoded without DEM as depicted in Fig. 3(b).

To solve such problem in TRI-DRRZ while still keeping the advantages of TRI and incorporated random switching and RZ operations, we propose TRI-DEMRZ in this paper. Figure 4 depicts the TRI-DEMRZ concept. It consists of a DEM decoder, a RZ decoder, and two sub-DACs, i.e. subDAC-1 and subDAC-2. In each odd clock phase, subDAC-1 generates an NRZ output under the control of the DEM decoder, and subDAC-2 returns to zero under the control of the RZ decoder. In each even clock phase, subDAC-1 and subDAC-2 interchange actions. It is noted that the RZ decoding needs not to be random, as is the case in DMRZ. Figure 4 also compares the waveforms of DMRZ and TRI-DEMRZ.
Fig. 4

The function diagram of TRI-DEMRZ. a Implementation; b Transient waveform examples [4]

Same as the evolvement from DRRZ to TRI-DRRZ, the proposed TRI-DEMRZ has essential advantages over DMRZ, including (1) the relaxation of settling-time requirements, (2) the increase of signal energy and more suppression of image tones, and (3) higher SFDR due to higher signal power but the same total number of randomized switching activities and corresponding switching glitches.

It is noted that the total number of switching activities in TRI-DEMRZ is the same as DMRZ, DRRZ, and TRI-DRRZ, all higher than NRZ. Detailed analysis in this aspect has been provided in [3]. Such behavior results in higher noise level than NRZ DACs, which is one side effect of these techniques. Another side effect of TRI-DEMRZ is the doubled number of current sources, which is the main drawback of interleaving techniques. However, compared with the traditional uncalibrated interleaved DACs, e.g. the DAC with TRI-DRRZ in [3], the area of each sub-DACs could be smaller with TRI-DEMRZ. This is because the dynamic element matching in TRI-DEMRZ transforms the mismatch-caused harmonics or tones into noise with lower requirement on the area for current source matching [13].

Summarizing the discussions above, TRI-DEMRZ significantly extends the design space of wideband high-SFDR DACs by trading additional randomized switch activities and chip area for a higher SFDR. Table 1 summarizes the performance comparisons between NRZ, DRRZ, DMRZ, TRI-DRRZ and TRI-DEMRZ.
Table 1

Comparisons between TRI-DEMRZ and others with NRZ as the baseline







Settling requirement

Open image in new window

Open image in new window

Output signal power

Open image in new window

Open image in new window

Image suppressiona

Open image in new window

Open image in new window

Switch driving power

Open image in new window

Open image in new window

Open image in new window

Open image in new window

Static mismatch averaging

Open image in new window

Open image in new window

Chip area

Open image in new window Open image in new window

Open image in new window





“☺”, “ Open image in new window ”, and “–”  represent better, worse, and no significantly different results, respectively

aThe image represents the signal image in the 2nd Nyquist spectrum region

bSubject to signal power and distortions by mismatch and switching glitches

3 Channel mismatch randomization

This section reveals and studies the channel mismatch randomization property of TRI-DEMRZ. The use of DEM allows each sub-DACs to be smaller size, which on the contrary deteriorates the channel mismatch for interleaving technique. Fortunately, the use of DEM not only randomizes the static mismatch inside each sub-DAC but also randomizes the channel mismatch between two sub-DACs at the same time. Since DEM introduces redundant combination of current sources, the use of DEM equivalently improves the alternative selection for sub-DACs compared with the interleaving without DEM [39]. This property can help to obscure the channel mismatch between the two sub-DACs. The detailed derivation and analyses of this feature are provided in this section.

3.1 Mathematical model

For simplicity, the input and output of a single channel DAC with DEM are represented by x(n) and y(n), respectively. According to [40], the time-average autocorrelation \( \bar{R}_{yy} \left( k \right) \) of the output \( y\left( n \right) \) in the single channel DAC with N current sources is:
$$ \bar{R}_{yy} \left( k \right) = \left( {1 + \alpha } \right)\bar{R}_{xx} \left( k \right) + \bar{\beta } + \bar{\sigma }^{2} \delta \left( k \right) , $$
with probability 1, where \( \bar{R}_{xx} \left( k \right) \) is the time-average autocorrelation of input \( x\left( n \right) \), \( \delta \left( k \right) \) is the Kronecker delta function which is non-zero only when k is 0. The coefficient in (1): \( \upalpha \), \( \bar{\beta } \), \( \bar{\sigma }^{2} \) are constant and the expression for them are provided in [40]:
$$ \upalpha = e_{0} \left( {2 + e_{0} } \right) , $$
$$ \bar{\beta } = 2e_{1} \left( {1 + e_{0} } \right)\bar{M}_{x} + e_{1}^{2} , $$
$$ \bar{\sigma }^{2} = \frac{1}{N - 1}\left[ {e_{0}^{2} - \frac{{\left( {e_{h} - e_{l} } \right)^{T} \left( {e_{h} - e_{l} } \right)}}{{N\Delta^{2} }}} \right].\left[ {x_{min} x_{max} + \bar{R}_{xx} \left( 0 \right) - \left( {x_{min} + x_{max} } \right)\bar{M}_{x} } \right] $$
where \( \bar{M}_{x} \) is the time-average mean of input \( {\text{x}}\left( n \right) \), while \( \Delta \) is the step-size of the DAC, and
$$ e_{0} = \frac{1}{N\Delta }\left( {1^{T} e_{h} - 1^{T} e_{l} } \right) , $$
$$ e_{1} = \frac{1}{N\Delta }\left( {x_{min} 1^{T} e_{h} - x_{max} 1^{T} e_{l} } \right) , $$
where \( e_{h} \) and \( e_{l} \) represent the conversion errors of each current sources in DAC, and
$$ e_{h} = \left[ {\begin{array}{*{20}c} {e_{{h_{1} }} } \\ \vdots \\ {e_{{h_{N} }} } \\ \end{array} } \right],\;e_{l} = \left[ {\begin{array}{*{20}c} {e_{{l_{1} }} } \\ \vdots \\ {e_{{l_{N} }} } \\ \end{array} } \right],\;1^{T} = \left[ {1 \cdots 1} \right] $$
while \( e_{{h_{i} }} \) and \( e_{{l_{i} }} \) are the errors of the \( i \)th current sources.

Based on the DEM analysis for one single channel DAC, the rest of this subsection provides the analysis of channel mismatch randomization incorporating DEM and interleaving.

Let \( x\left( n \right) \) to be the input digital code, \( y_{1} \left( n \right) \) and \( y_{2} \left( n \right) \) to represent the function of each sub-DACs with DEM, both of which is unary decoded with N current sources and obeys (1), and let \( y\left( n \right) \) to be the interleaved output of the DAC with TRI-DEMRZ, which can be represented as:
$$ y\left( n \right) = T\left( n \right)y_{1} \left( n \right) + \left( {1 - T\left( n \right)} \right)y_{2} \left( n \right) , $$
where \( T\left( n \right) \) represents the switching function between each sub-DAC and changes between 0 and 1 each clock cycle in turn.
Firstly, the cross-correlation between the output \( y\left( n \right) \) and the channel mismatch \( \varepsilon \left( n \right) = y_{1} \left( n \right) - y_{2} \left( n \right) \) is derived:
$$ R_{y,\varepsilon } \left( {n,k} \right) = E\left[ {y\left( n \right)\left( { y_{1} \left( {n + k} \right) - y_{2} \left( {n + k} \right)} \right)} \right] . $$
Substituting (5) into (6), collecting terms gives
$$ \begin{aligned} R_{y,\varepsilon } \left( {n,k} \right) = & E\left[ {y_{2} \left( n \right)y_{1} \left( {n + k} \right)} \right] - R_{{y_{2} ,y_{2} }} \left( {n,k} \right) \\ & + T\left( n \right)\left[ {R_{{y_{1} ,y_{1} }} \left( {n,k} \right) + R_{{y_{2} ,y_{2} }} \left( {n,k} \right)} \right. - E\left[ {y_{1} \left( n \right)y_{2} \left( {n + k} \right)} \right] - \left. {E\left[ {y_{2} \left( n \right)y_{1} \left( {n + k} \right)} \right]} \right] \\ \end{aligned} . $$
Assuming that each sub-DAC is independent of one another gives
$$ E\left[ {y_{2} \left( n \right)y_{1} \left( {n + k} \right)} \right] = E\left[ {y_{2} \left( n \right)\left] E \right[y_{1} \left( {n + k} \right)} \right] , $$
$$ E\left[ {y_{1} \left( n \right)y_{2} \left( {n + k} \right)} \right] = E\left[ {y_{1} \left( n \right)\left] E \right[y_{2} \left( {n + k} \right)} \right] . $$
Using the conclusion in [40], we have
$$ E\left[ {y_{2} \left( n \right)} \right] = x\left( n \right)\left( {1 + \mu_{0,2} } \right) + \mu_{1,2} , $$
$$ E\left[ {y_{2} \left( {n + k} \right)} \right] = x\left( {n + k} \right)\left( {1 + \mu_{0,2} } \right) + \mu_{1,2} , $$
$$ E\left[ {y_{1} \left( n \right)} \right] = x\left( n \right)\left( {1 + \mu_{0,1} } \right) + \mu_{1,1} , $$
$$ E\left[ {y_{1} \left( {n + k} \right)} \right] = x\left( {n + k} \right)\left( {1 + \mu_{0,1} } \right) + \mu_{1,1} , $$
where the \( \mu_{0,i} \) and \( \mu_{1,i} \) is the parameter in the \( i \)th sub-DACs corresponding to \( e_{0} \) and \( e_{1} \) in (3a) and (3b).
Based on the definition in [40], the time-average cross-correlation between output and channel mismatch is:
$$ \bar{R}_{y,\varepsilon } \left( k \right) = \mathop {\lim }\limits_{P \to \infty } \frac{1}{P}\mathop \sum \limits_{n = 1}^{P} R_{y,\varepsilon } \left( {n,k} \right) . $$
Substituting (7), (8), (9) into (10), collecting the terms gives
$$ \bar{R}_{y,\varepsilon } \left( k \right) = \frac{1}{2}\left[ {\bar{R}_{{y_{1} ,y_{1} }} \left( k \right) - \bar{R}_{{y_{2} ,y_{2} }} \left( k \right)} \right] . $$
Substituting (1) into (11), collecting the terms gives
$$ \bar{R}_{y,\varepsilon } \left( k \right) = \frac{1}{2}\left[ {\left( {\alpha_{DAC1} - \alpha_{DAC2} } \right)\bar{R}_{xx} \left( k \right) + \left( {\bar{\beta }_{DAC1} - \bar{\beta }_{DAC2} } \right) + \left( {\bar{\sigma }_{DAC1}^{2} - \bar{\sigma }_{DAC2}^{2} } \right)\delta \left( k \right)} \right] . $$
Using the definition in (2)–(4), letting \( e_{{l_{i} }} \) be zero and letting \( \delta_{k,i} \) represents the \( i \)th current mismatch in the \( k \)th sub-DAC channel, we can get this conclusion that when the mismatch of each sub-DACs meets the requirement as follows:
$$ \mathop \sum \limits_{i = 1}^{N} \delta_{1,i} = \mathop \sum \limits_{i = 1}^{N} \delta_{2,i} , $$
$$ \mathop \sum \limits_{i = 1}^{N} \left( {\delta_{1,i} } \right)^{2} = \mathop \sum \limits_{i = 1}^{N} \left( {\delta_{2,i} } \right)^{2} , $$
the time-average cross-correlation between output and channel mismatch is zero, which, in the theory of random process, means that the output is independent of channel mismatch and the image tone is randomized into noise. The analysis above reveals that to ensure the effectiveness of channel mismatch randomization, the physical location of two corresponding current sources, \( \delta_{1,i} \) and \( \delta_{2,i} \) from two sub-DACs, should be as close as possible. In this way, the gradient mismatch will have less impact on (13a).

3.2 Numerical simulation

As analyzed in the previous subsection, when the two unary-decoded sub-DACs in TRI-DEMRZ meet the requirement in (13), i.e. the same mean value and power of the current source mismatch in each sub-DAC, the image tone due to the channel mismatch can be completely eliminated. In practical, considering inevitable variations and also widely used layout techniques like common-centroid layout schemes in [41] for mismatch control, we have analyzed the impact of a certain amount of deviation from the requirement in (13). Numerical simulation results are provided in Fig. 5, in which the normalized power of the image tone due to different amounts of deviation in (13) is compared between TRI-DEMRZ and conventional interleaving DAC without DEM. In Fig. 5, thirteen pairs of current sources are randomly generated using MATLAB normal distribution generation function “normrnd” with different mean and standard deviation to simulate the deviation in (13). For each sample, the arithmetic sum deviation is the absolute value of the deviation in (13a) which is normalized to one LSB:
$$ \left| {\mathop \sum \limits_{i = 1}^{N} \delta_{1,i} - \mathop \sum \limits_{i = 1}^{N} \delta_{2,i} } \right|/1LSB , $$
while the quadratic sum deviation in (13b) is:
$$ \left| {\mathop \sum \limits_{i = 1}^{N} \left( {\delta_{1,i} } \right)^{2} - \mathop \sum \limits_{i = 1}^{N} \left( {\delta_{2,i} } \right)^{2} } \right|/\left( {1LSB} \right)^{2} . $$
Fig. 5

Image tone power versus channel mismatch deviation in interleaving DAC with DEM ON and OFF. For each samples the image tone is normalized to signal power, which is 0 dBm, while the corresponding deviation is normalized to LSB for arithmetic sum deviation and LSB2 for quadratic sum deviation

For example, the 11th sample in Fig. 5 has normalized arithmetic sum deviation near 2LSB while the quadratic sum deviation is around 10LSB2 and for the 4th sample, they are near zero LSB and 10LSB2 separately.

Sample 1 to 4 in Fig. 5 confirm that TRI-DEMRZ is insensitive to the quadratic sum deviation and shows 10–20 dBc image suppression compared with the interleaving without DEM. It means that the value of (14b) has a few influence in the performance of TRI-DEMRZ in channel mismatch randomization as depicted in Fig. 6(a). However, sample 5 to 8 reveal that there is more critical requirement in (14a) to guarantee the performance of TRI-DEMRZ. This is reasonable that when there is obvious mean value deviation in (14a), even under the time average of DEM, the offset between each sub-DACs still exists as depicted in Fig. 6(b). In those cases, if the gradient channel mismatches are all positive or negative, the averaged channel mismatch is larger than that of interleaving without DEM at low amplitude, which may make the image tone worse for TRI-DEMRZ, as shown in sample 8 and sample 10. From sample 9 to sample 13, where the arithmetic sum deviation keeps almost the same and the quadratic sum deviation increases, the image tone of interleaving without DEM deteriorates worse, which again proves the advantages of incorporating DEM with interleaving.
Fig. 6

The conversion difference in interleaving with and without DEM in mismatch distribution example 1 (a) and example 2 (b)

In summary, TRI-DEMRZ incorporating DEM and interleaving not only improves the linearity of each sub-DACs, but also suppresses the image tone caused by channel mismatch in interleaving. Besides, the simulation above emphasizes the importance of (13a) in the design of DAC using TRI-DEMRZ.

4 Implementation and experiment

This section provides the implementation of TRI-DEMRZ and the experimental results of the fabricated experimental DAC.

4.1 Chip implementation

To verify the effectiveness of TRI-DEMRZ, a 14-bit 500-MS/s current-steering DAC in 65 nm CMOS was implemented. The DAC structure is shown in Fig. 7(a), including a current source and switch array, a latch array, a TRI-DEMRZ decoder, and a clock generator. The DAC is segmented into 6B + 4B + 4B. This DAC has 1.2 V digital power supply and 2.5 V for the current source and switch arrays. The full-scale current output is 32 mA and the differential AC load is 50 Ω. The chip photograph of the fabricated DAC is shown in Fig. 7(b). The active area is 0.42 mm2, and the entire chip outline is 1.9 mm × 1.1 mm.
Fig. 7

Chip implementation a the structure of this 14-bit DAC with TRI-DEMRZ and b micrograph of the fabricated 14-bit DAC using 65 nm process

The complementary switched current source (CSCS) depicted in Fig. 8 is employed for the MSB and ULSB segments to reduce the code-dependent load variations caused by the finite output impedance [3, 4]. Considering the output impedance of LSB branches is not the main bottleneck, CSCS is not applied to the LSB segment. For an MSB CSCS unit, the main current I0 is 320 μA and the complementary current I0’ is 64 μA, forming a differential output of 256 μA. In ULSB, the main current and the complementary current are 32 μA and 16 μA, respectively, forming a differential output of 16 μA. Both MSB and ULSB are based on the same 16 µA current source unit for matching performance. Another 16 μA current unit is split into 16 unary smaller current sources and 15 of them are used to implement the four LSBs, and the rest one as dummy. As discussed in Section “Static mismatches and switching distortions”, with the DEM technique to mitigate the impact of transistor mismatches, a smaller transistor size of 4.8 μm width and 4.5 μm length is adopted for an MSB current source unit. Such sizing provides 90% integral nonlinearity (INL) yield without DEM. The cascade current source transistors, the switches, as well as the top cascoded transistors, are implemented with the shortest gate length to reduce the parasitic capacitance. A smaller transistor size also helps to reduce the timing errors in the switching driving circuitry and the output current tree.
Fig. 8

The CSCS unit [3, 4]

A linear feedback shift register (LFSR) is used as PRNG, and a random rotation-based binary-weighted selection (RRBS) scheme in [42] is employed for the DEM decoder.

For the sub-DAC which returns to zero, the PRNG randomly selects 32 MSB current sources and 15 ULSB current sources to the DAC’s positive output port and the remaining current sources in MSB and ULSB to the negative output port. Through this way, the differential output of this sub DAC is almost zero with a DC offset of only one LSB which has very little impact on the dynamic performance and is negligible in most applications because this DC offset is isolated by the transformer used for AC differential-to-single conversion [3].

For the sub-DAC which performs the net output according the digital input, the RRBS shown in Fig. 9 is used to implement the DEM decoder. A 3-bit RRBS full decoder implementation example is illustrated in Fig. 9(a) [42]. A 4-bit RRBS full decoder could also be implemented in the same way. The ULSB DEM decoder in this DAC is such a 4-bit RRBS full decoder. To avoid excessively long routing distance and complexity, the construction of the 6-bit MSB RRBS decoder is simplified by reusing the 4-bit RRBS decoder and properly arrange the connection, as illustrated in Fig. 9(b).
Fig. 9

The structure of a 3-bit RRBS in (a) and a simplified 6-bit RRBS in (b) implemented with four 4-bit RRBS and one 2-bit RRBS [4]

4.2 Measurement results

Figure 10 shows the measured INL performance. With TRI-DEMRZ disabled, the DAC operates with only one sub-DAC responding to the input digits in a binary-weighted switching pattern. The measured INL is + 5/− 7 LSB, as shown in Fig. 10(a). The average INL is also measured with TRI-DEMRZ on. Due to the complexity of measurement, in this case, only the MSB segment was measured. As shown in Fig. 10(b), it is reduced significantly to only + 1.2/− 1.2 LSB after 500 cycles of DEM randomization, which proves the effectiveness of the DEM decoder.
Fig. 10

The measured INL curves in (a) with 14-bit full-range input code, and the average INL curves in (b) of the 6-bit MSB with TRI-DEMRZ on for 30 (gray), 80 (black), and 500 (blue) clock samples (Color figure online)

Figure 11(a), (b) shows the measured output spectra at a 250-MS/s sampling rate with TRI-DEMRZ disabled. The measured SFDR is 70.4 dB at 5.8 MHz and 61.0 dB at 122 MHz, as shown in Fig. 11(a), (b), respectively. When the TRI-DEMRZ is on, the harmonic is suppressed and the SFDR reaches 90.0 dB at 5.8 MHz and 79.2 dB at 122 MHz, as shown in Fig. 11(c), (d), respectively. Such improvement is brought by the TRI-DEMRZ method with signal-independent switching and channel mismatch randomization. At low signal frequencies, the SFDR is mainly determined by the matching property of the current sources and interleaving channels, and TRI-DEMRZ is able to effectively average out most current source mismatches, leading to a higher SFDR. At a higher frequency, although the static mismatch averaging improvement is less, TRI-DEMRZ is able to significantly reduce the distortions induced by the code-dependent switching glitches, which dominate the SFDR at a high frequency. Figure 12 plots the measured SFDR versus the signal frequency at 250-MS/s and 500-MS/s. At 250-MS/s, the observed SFDR improvement within the entire Nyquist band varies from 11.5 dB to more than 20.0 dB. At 500-MS/s, this DAC reaches more than 70 dB SFDR within 211 MHz band. It is noted that, at 500-MS/s, the SFDR with TRI-DEMRZ turned on at around 40 MHz is lower than adjacent measurement results in Fig. 12. While similar phenomena and explanations can be found in both literature and products [2, 3, 43], here it may be caused by the signal integrity problem at the DAC input interface. The experimental measurement setup utilizes a single-ended full-swing CMOS parallel interface, and the alignment of the parallel input digital bits is thus very critical for a lower bit error rate. As we experience in the experiments, slightly adjusting the delay of some digital input bits can affect the harmonic tones significantly. While a number of delay settings have been applied in the experiments, the alignment may still be not satisfactory for the measurement around 40 MHz in Fig. 12.
Fig. 11

The measured output spectrum at 250 MS/s with TRI-DEMRZ disabled in (a, b), and TRI-DEMRZ enabled in (c, d)

Fig. 12

The measured SFDR versus the signal frequency when TRI-DEMRZ enabled and disabled

Table 2 provides a summary of the performance of the fabricated DAC. Table 3 compares the performance of the fabricated DAC with the state-of-the-art designs. Although the SFDR of this work is lower than [44], the savings from not using the oversampling rate and off-chip calibration techniques reduce the complexity and make a wideband DAC design less challenging. Although the sampling frequency of this work is not as high as other works due to the limitations by the CMOS single-ended I/O signal integrity, in the near-Nyquist band of this design, the SFDR of this DAC is higher than [2, 3, 38]. To the best of the authors’ knowledge, this work is the only reported design in literature that achieves 90 dB SFDR without calibration or oversampling techniques. Future work of integrating calibration techniques would potentially enable an even higher SFDR. To evaluate the overall power efficiency of this DAC, the widely used figure-of-merit (FOM) [3] is provided in Table 3. Considering the sampling rate, SFDR at a low signal frequency, SFDR near the Nyquist, the signal power, and the DAC power consumption, the FOM of this DAC is higher than the designs [2, 3, 38] with similar technique in Table 3.
Table 2

Measured performance of the proposed TRI-DEMRZ DAC


CMOS 65 nm


14 bits

Clock rate



> 70 dB within 211 MHz


+ 5/− 7 LSB

Supply voltage

1.2 V/2.5 V

Power consumption

106 mW

Active area

0.42 mm2

Table 3

Comparisons with state-of-the-art works


This work















Process (nm)






Core area (mm2)






Supply (V)






DAC power (mW)






Sampling rate (GS/s)






Resolution (bits)












Full-scale current (mA)












SFDRfs/2 (dB)






FOM (104Hz/mW)a






a\( {\text{FOM}} = 2^{{\left( {{\text{SFDR}}_{\text{LF}} - 1.76} \right)/6.02}} \times 2^{{\left( {{\text{SFDR}}_{{f_{s} /2}} - 1.76} \right)/6.02}} \times f_{s} /\left( {P_{\text{DAC}} - P_{\text{sig}} } \right) \), where \( P_{\text{DAC}} \) and \( P_{\text{sig}} \) are the power of the entire DAC and the output signal, respectively

bMeasured and calculated @ 0.25 GS/s

5 Conclusion

This paper has revealed that, other than simply incorporating DMRZ and time-relaxed interleaving, TRI-DEMRZ shows more merits. In addition to mitigating the non-linear distortions caused by code-dependent switching activities, TRI-DEMRZ provides an effective method to deal with the channel mismatch in interleaving architectures. The exploration of TRI-DEMRZ has significantly extended the design space of wideband high-SFDR DACs by trading additional randomized switch activities and chip area for a higher SFDR. In addition to the theoretical analysis, a 14-bit 500-MS/s current-steering DAC in 65 nm is implemented. The measured SFDR improvement further verifies the effectiveness of TRI-DEMRZ.



This work was supported in part by the National High Technology Research and Development Program of China (No. 2013AA014103) and in part by the NSFC under Grant #61720106013 and #61532017.


  1. 1.
    Chan, K. L., Zhu, J., & Galton, I. (2008). Dynamic element matching to prevent nonlinear distortion from pulse-shape mismatches in high-resolution DACs. IEEE Journal of Solid-State Circuits, 43(9), 2067–2078.CrossRefGoogle Scholar
  2. 2.
    Lin, W.-T., & Kuo, T.-H. (2013). A 12 b 1.6 GS/s 40 mW DAC in 40 nm CMOS with > 70 dB SFDR over entire Nyquist bandwidth. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 474–475).Google Scholar
  3. 3.
    Li, X., Wei, Q., Xu, Z., Liu, J., Wang, H., & Yang, H. (2014). A 14 bit 500 MS/s CMOS DAC using complementary switched current sources and time-relaxed interleaving DRRZ. IEEE Transactions on Circuits Systems I: Regular Papers, 61(8), 2337–2347.CrossRefGoogle Scholar
  4. 4.
    Liu, J., Li, X., Wei, Q., & Yang, H. (2015). A 14-bit 1.0-GS/s dynamic element matching DAC with > 80 dB SFDR up to the Nyquist. In IEEE international symposium on circuits and systems (ISCAS) (pp. 1026–1029).Google Scholar
  5. 5.
    Van de Sande, F., et al. (2012). A 7.2 GSa/s, 14 bit or 12 GSa/s, 12 bit signal generator on a chip in a 165 GHz fT BiCMOS process. IEEE Journal of Solid- State Circuits, 47(4), 1003–1012.CrossRefGoogle Scholar
  6. 6.
    McCue, J. J., et al. (2016). A time-interleaved multimode ΔΣ RF-DAC for direct digital-to-RF synthesis. IEEE Journal of Solid-State Circuits, 51(5), 1109–1124.CrossRefGoogle Scholar
  7. 7.
    Bhide, A., & Alvandpour, A. (2015). An 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC for 60 GHz radio in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 50(10), 2306–2318.CrossRefGoogle Scholar
  8. 8.
    Chandra, G., & Seedher, A. (2008). On the spectral tones in a digital-analog converter due to mismatch and flicker noise. IEEE Transactions on Circuits Systems II: Express Briefs, 55(7), 619–623.CrossRefGoogle Scholar
  9. 9.
    Bruce, J. W., & Stubberud, P. (1999). An analysis of harmonic distortion and integral nonlinearity in digital to analog converters. In 42-nd midwest symposium on circuits and systems (pp. 470–473).Google Scholar
  10. 10.
    Cong, Y., & Geiger, R. L. (2003). A 1.5 V 14 b 100 MS/s self-calibrated DAC. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 128–130).Google Scholar
  11. 11.
    Cong, Y., & Geiger, R. L. (2000). Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays. IEEE Transactions on Circuits Systems II: Express Briefs, 47(7), 585–595.CrossRefGoogle Scholar
  12. 12.
    Van der Plas, G. A. M., et al. (1999). A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE Journal of Solid-State Circuits, 34(12), 1708–1718.CrossRefGoogle Scholar
  13. 13.
    Pelgrom, M. J. M., Duinmaijer, A. C. J., & Welbers, A. P. G. (1989). Matching properties of MOS transistors. IEEE Journal of Solid-State Circuits, 24(5), 1433–1439.CrossRefGoogle Scholar
  14. 14.
    Kuo, K.-C., & Wu, C.-W. (2011). A switching sequence for linear gradient error compensation in the DAC design. IEEE Transactions on Circuits Systems II: Express Briefs, 58(8), 502–506.CrossRefGoogle Scholar
  15. 15.
    Chiu, Y. (2015). Digital adaptive calibration of data converters using independent component analysis. In G. E. Pfander (Ed.), Sampling theory, a renaissance (pp. 485–517). New York: Springer.Google Scholar
  16. 16.
    Wang, R., Huang, D., He, T., Chen, J., You, Y., & Gui, P. (2015). Effect of OPAMP input offset on continuous-time ΔΣ modulators with current-mode DACs. IEEE Transactions on Circuits Systems I: Regular Papers, 62(7), 1699–1706.MathSciNetCrossRefGoogle Scholar
  17. 17.
    Wang, R., et al. (2015). A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration. In IEEE international midwest symposium on circuits and systems (MWSCAS) (pp. 1–4).Google Scholar
  18. 18.
    Bugeja, A. R., & Song, B.-S. (2000). A self-trimming 14-b 100-MS/s CMOS DAC. IEEE Journal of Solid-State Circuits, 35(12), 1841–1852.CrossRefGoogle Scholar
  19. 19.
    Lin, C.-H., & Bult, K. (1998). A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2. IEEE Journal of Solid-State Circuits, 33(12), 1948–1958.CrossRefGoogle Scholar
  20. 20.
    Carley, L. R. (1989). A noise-shaping coder topology for 15+ bit converters. IEEE Journal of Solid State Circuits, 24(2), 267–273.CrossRefGoogle Scholar
  21. 21.
    Xu, Z., et al. (2014). A 14-bit 500-MS/s DAC with digital background calibration. Journal of Semiconductors, 35(3), 109–113.CrossRefGoogle Scholar
  22. 22.
    Van de Vel, H., et al. (2014). A 240 mW 16 b 3.2 GS/s DAC in 65 nm CMOS with < − 80 dBc IM3 up to 600 MHz. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 206–207).Google Scholar
  23. 23.
    Schafferer, B., & Adams, R. (2004). A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC for multi-carrier applications. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 360–362).Google Scholar
  24. 24.
    Li, X., Fan, H., Wei, Q., Xu, Z., Liu, J., & Yang, H. (2013). A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter. Journal of Semiconductors, 34(8), 155–161.Google Scholar
  25. 25.
    Palmers, P., & Steyaert, M. S. J. (2010). A 10-bit 1.6-GS/s 27-mW current-steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS. IEEE Transactions on Circuits Systems I: Regular Papers, 57(11), 2870–2879.MathSciNetCrossRefGoogle Scholar
  26. 26.
    Li, X., Wei, Q., & Yang, H. (2011). Code-independent output impedance: A new approach to increasing the linearity of current-steering DACs. In IEEE international conference on electronics, circuits, and systems (ICECS) (pp. 216–219).Google Scholar
  27. 27.
    Clara, M. (2013). Dynamic linearity. In K. Itoh, T. H. Lee, T. Sakurai, W. Sansen, D. Schmitt-Landsiedel (Eds.), High-performance D/A-converters application to digital transceivers (pp. 97–132). New York: Springer.Google Scholar
  28. 28.
    Risbo, L., et al. (2011). Digital approaches to ISI-mitigation in high-resolution oversampled multi-level D/A converters. IEEE Journal of Solid-State Circuits, 46(12), 2892–2903.CrossRefGoogle Scholar
  29. 29.
    Sanyal, A., Wang, P., & Sun, N. (2014). A thermometer-like mismatch shaping technique with minimum element transition activity for multibit ΔΣ DACs. IEEE Transactions on Circuits Systems II: Express Briefs, 61(7), 461–465.CrossRefGoogle Scholar
  30. 30.
    Tseng, W.-H., Wu, J. T., & Chu, Y. C. (2011). A CMOS 8-bit 1.6-GS/s DAC with digital random return-to-zero. IEEE Transactions on Circuits Systems II: Express Briefs, 58(1), 1–5.CrossRefGoogle Scholar
  31. 31.
    Park, S., Kim, G., Park, S.-C., & Kim, W. (2002). A digital-to-analog converter based on differential-quad switching. IEEE Journal of Solid-State Circuits, 37(10), 1335–1338.CrossRefGoogle Scholar
  32. 32.
    Thomas, K. P. J., Rana, R. S., & Lian, Y. (2005). A 1 GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion. In Proceedings of IEEE Asia and South Pacific design automation conference (ASP-DAC) (pp. 665–670).Google Scholar
  33. 33.
    Choe, M.-J., Baek, K.-H., & Teshome, M. (2005). A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation. IEEE Journal of Solid-State Circuits, 40(12), 2456–2468.CrossRefGoogle Scholar
  34. 34.
    Huang, Q., Francese, P. A. Martelli, C. & Nielsen, J. (2004). A 200 MS/s 14 b 97 mW DAC in 0.18 μm CMOS. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 364–365).Google Scholar
  35. 35.
    Chen, T., & Gielen, G. G. E. (2006). The analysis and improvement of a current-steering DACs dynamic SFDR-I: The cell-dependent delay differences. IEEE Transactions on Circuits Systems I: Regular Papers, 53(1), 3–15.CrossRefGoogle Scholar
  36. 36.
    Shui, T., Schreier, R., & Hudson, F. (1999). Mismatch shaping for a current-mode multibit delta-sigma DAC. IEEE Journal of Solid-State Circuits, 34(3), 331–338.CrossRefGoogle Scholar
  37. 37.
    Schofield, W., Mercer, D., & Onge, L. S. (2003). A 16 b 400 MS/s DAC with < − 80 dBc IMD to 300 MHz and < − 160 dBm/Hz noise power spectral density. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 126–127).Google Scholar
  38. 38.
    Tseng, W.-H., Fan, C.-W., & Wu, J.-T. (2011). A 12-bit 1.25-GS/s DAC in 90 nm CMOS with > 70 dB SFDR up to 500 MHz. IEEE Journal of Solid-State Circuits, 46(12), 2845–2856.CrossRefGoogle Scholar
  39. 39.
    Olieman, E., Annema, A., & Nauta, A. (2014). A 110 mW, 0.04 mm2, 11 GS/s 9-bit interleaved DAC in 28 nm FDSOI with > 50 dB SFDR across Nyquist. In IEEE symposium on VLSI circuits digest of technical papers (pp. 1–2).Google Scholar
  40. 40.
    Galton, I., & Carbone, P. (1995). A rigorous error analysis of D/A conversion with dynamic element matching. IEEE Transactions on Circuits Systems II: Analog and Digital Signal Processing, 42(12), 763–772.CrossRefGoogle Scholar
  41. 41.
    Soares, C. F. T., & Petraglia, A. (2015). Automatic placement to improve capacitance matching using a generalized common-centroid layout and spatial correlation optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(10), 1691–1695.CrossRefGoogle Scholar
  42. 42.
    Lin, W.-T., & Kuo, T.-H. (2012). A compact dynamic-performance-improved current-steering DAC with random rotation-based binary-weighted selection. IEEE Journal of Solid-State Circuits, 47(2), 444–453.CrossRefGoogle Scholar
  43. 43.
    Lin, C.-H., et al. (2009). A 12 b 2.9 GS/s DAC with IM3 < − 60 dBc Beyond 1 GHz in 65 nm CMOS. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 74–75).Google Scholar
  44. 44.
    Su, S., & Chen, M. S.-W. (2016). A 12-bit 2 GS/s dual-rate hybrid DAC with pulse-error pre-distortion and in-band noise cancellation achieving > 74 dBc SFDR and < − 80 dBc IM3 up to 1 GHz in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 51(12), 2963–2978.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Longqiang Lai
    • 1
  • Xueqing Li
    • 1
  • Jianan Liu
    • 2
  • Huazhong Yang
    • 1
  1. 1.Department of Electronics EngineeringTsinghua UniversityBeijingChina
  2. 2.Xiaomi Inc.BeijingChina

Personalised recommendations