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A 14-bit 500-MS/s DAC with 211-MHz 70 dB SFDR bandwidth using TRI-DEMRZ

  • Longqiang Lai
  • Xueqing Li
  • Jianan Liu
  • Huazhong Yang
Article
  • 87 Downloads

Abstract

Time-relaxed interleaving dynamic element matching return-to-zero (TRI-DEMRZ) is proposed and verified in this paper to improve the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs). It incorporates time-relaxed interleaving (TRI), return-to-zero, and the dynamic-element-matching techniques, in a way that fosters the strength of each technique. As analyzed in this paper, merits beyond the combination of these techniques could be achieved. Firstly, TRI-DEMRZ provides a new dimension in the space domain, rather than the time domain, to explore the methods of mitigating nonlinear switching distortions. Secondly, this paper proves that, the image tone caused by typical channel mismatches between interleaved sub-DACs can be randomized into noise with TRI-DEMRZ. Circuit simulations and analysis are provided. An experimental 14-bit 500-MS/s current-steering DAC in 65 nm CMOS has been fabricated and measured, showing 81 dB SFDR at 5.5 MHz and more than 70 dB SFDR up to 211 MHz bandwidth. The SFDR improvement achieved by TRI-DEMRZ is more than 10 dB, which further verifies the effectiveness of TRI-DEMRZ.

Keywords

Digital-to-analog converter (DAC) Dynamic element matching (DEM) Channel mismatch Time-relaxed interleaving Current-steering 

Notes

Acknowledgements

This work was supported in part by the National High Technology Research and Development Program of China (No. 2013AA014103) and in part by the NSFC under Grant #61720106013 and #61532017.

References

  1. 1.
    Chan, K. L., Zhu, J., & Galton, I. (2008). Dynamic element matching to prevent nonlinear distortion from pulse-shape mismatches in high-resolution DACs. IEEE Journal of Solid-State Circuits, 43(9), 2067–2078.CrossRefGoogle Scholar
  2. 2.
    Lin, W.-T., & Kuo, T.-H. (2013). A 12 b 1.6 GS/s 40 mW DAC in 40 nm CMOS with > 70 dB SFDR over entire Nyquist bandwidth. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 474–475).Google Scholar
  3. 3.
    Li, X., Wei, Q., Xu, Z., Liu, J., Wang, H., & Yang, H. (2014). A 14 bit 500 MS/s CMOS DAC using complementary switched current sources and time-relaxed interleaving DRRZ. IEEE Transactions on Circuits Systems I: Regular Papers, 61(8), 2337–2347.CrossRefGoogle Scholar
  4. 4.
    Liu, J., Li, X., Wei, Q., & Yang, H. (2015). A 14-bit 1.0-GS/s dynamic element matching DAC with > 80 dB SFDR up to the Nyquist. In IEEE international symposium on circuits and systems (ISCAS) (pp. 1026–1029).Google Scholar
  5. 5.
    Van de Sande, F., et al. (2012). A 7.2 GSa/s, 14 bit or 12 GSa/s, 12 bit signal generator on a chip in a 165 GHz fT BiCMOS process. IEEE Journal of Solid- State Circuits, 47(4), 1003–1012.CrossRefGoogle Scholar
  6. 6.
    McCue, J. J., et al. (2016). A time-interleaved multimode ΔΣ RF-DAC for direct digital-to-RF synthesis. IEEE Journal of Solid-State Circuits, 51(5), 1109–1124.CrossRefGoogle Scholar
  7. 7.
    Bhide, A., & Alvandpour, A. (2015). An 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC for 60 GHz radio in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 50(10), 2306–2318.CrossRefGoogle Scholar
  8. 8.
    Chandra, G., & Seedher, A. (2008). On the spectral tones in a digital-analog converter due to mismatch and flicker noise. IEEE Transactions on Circuits Systems II: Express Briefs, 55(7), 619–623.CrossRefGoogle Scholar
  9. 9.
    Bruce, J. W., & Stubberud, P. (1999). An analysis of harmonic distortion and integral nonlinearity in digital to analog converters. In 42-nd midwest symposium on circuits and systems (pp. 470–473).Google Scholar
  10. 10.
    Cong, Y., & Geiger, R. L. (2003). A 1.5 V 14 b 100 MS/s self-calibrated DAC. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 128–130).Google Scholar
  11. 11.
    Cong, Y., & Geiger, R. L. (2000). Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays. IEEE Transactions on Circuits Systems II: Express Briefs, 47(7), 585–595.CrossRefGoogle Scholar
  12. 12.
    Van der Plas, G. A. M., et al. (1999). A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE Journal of Solid-State Circuits, 34(12), 1708–1718.CrossRefGoogle Scholar
  13. 13.
    Pelgrom, M. J. M., Duinmaijer, A. C. J., & Welbers, A. P. G. (1989). Matching properties of MOS transistors. IEEE Journal of Solid-State Circuits, 24(5), 1433–1439.CrossRefGoogle Scholar
  14. 14.
    Kuo, K.-C., & Wu, C.-W. (2011). A switching sequence for linear gradient error compensation in the DAC design. IEEE Transactions on Circuits Systems II: Express Briefs, 58(8), 502–506.CrossRefGoogle Scholar
  15. 15.
    Chiu, Y. (2015). Digital adaptive calibration of data converters using independent component analysis. In G. E. Pfander (Ed.), Sampling theory, a renaissance (pp. 485–517). New York: Springer.Google Scholar
  16. 16.
    Wang, R., Huang, D., He, T., Chen, J., You, Y., & Gui, P. (2015). Effect of OPAMP input offset on continuous-time ΔΣ modulators with current-mode DACs. IEEE Transactions on Circuits Systems I: Regular Papers, 62(7), 1699–1706.MathSciNetCrossRefGoogle Scholar
  17. 17.
    Wang, R., et al. (2015). A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration. In IEEE international midwest symposium on circuits and systems (MWSCAS) (pp. 1–4).Google Scholar
  18. 18.
    Bugeja, A. R., & Song, B.-S. (2000). A self-trimming 14-b 100-MS/s CMOS DAC. IEEE Journal of Solid-State Circuits, 35(12), 1841–1852.CrossRefGoogle Scholar
  19. 19.
    Lin, C.-H., & Bult, K. (1998). A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2. IEEE Journal of Solid-State Circuits, 33(12), 1948–1958.CrossRefGoogle Scholar
  20. 20.
    Carley, L. R. (1989). A noise-shaping coder topology for 15+ bit converters. IEEE Journal of Solid State Circuits, 24(2), 267–273.CrossRefGoogle Scholar
  21. 21.
    Xu, Z., et al. (2014). A 14-bit 500-MS/s DAC with digital background calibration. Journal of Semiconductors, 35(3), 109–113.CrossRefGoogle Scholar
  22. 22.
    Van de Vel, H., et al. (2014). A 240 mW 16 b 3.2 GS/s DAC in 65 nm CMOS with < − 80 dBc IM3 up to 600 MHz. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 206–207).Google Scholar
  23. 23.
    Schafferer, B., & Adams, R. (2004). A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC for multi-carrier applications. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 360–362).Google Scholar
  24. 24.
    Li, X., Fan, H., Wei, Q., Xu, Z., Liu, J., & Yang, H. (2013). A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter. Journal of Semiconductors, 34(8), 155–161.Google Scholar
  25. 25.
    Palmers, P., & Steyaert, M. S. J. (2010). A 10-bit 1.6-GS/s 27-mW current-steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS. IEEE Transactions on Circuits Systems I: Regular Papers, 57(11), 2870–2879.MathSciNetCrossRefGoogle Scholar
  26. 26.
    Li, X., Wei, Q., & Yang, H. (2011). Code-independent output impedance: A new approach to increasing the linearity of current-steering DACs. In IEEE international conference on electronics, circuits, and systems (ICECS) (pp. 216–219).Google Scholar
  27. 27.
    Clara, M. (2013). Dynamic linearity. In K. Itoh, T. H. Lee, T. Sakurai, W. Sansen, D. Schmitt-Landsiedel (Eds.), High-performance D/A-converters application to digital transceivers (pp. 97–132). New York: Springer.Google Scholar
  28. 28.
    Risbo, L., et al. (2011). Digital approaches to ISI-mitigation in high-resolution oversampled multi-level D/A converters. IEEE Journal of Solid-State Circuits, 46(12), 2892–2903.CrossRefGoogle Scholar
  29. 29.
    Sanyal, A., Wang, P., & Sun, N. (2014). A thermometer-like mismatch shaping technique with minimum element transition activity for multibit ΔΣ DACs. IEEE Transactions on Circuits Systems II: Express Briefs, 61(7), 461–465.CrossRefGoogle Scholar
  30. 30.
    Tseng, W.-H., Wu, J. T., & Chu, Y. C. (2011). A CMOS 8-bit 1.6-GS/s DAC with digital random return-to-zero. IEEE Transactions on Circuits Systems II: Express Briefs, 58(1), 1–5.CrossRefGoogle Scholar
  31. 31.
    Park, S., Kim, G., Park, S.-C., & Kim, W. (2002). A digital-to-analog converter based on differential-quad switching. IEEE Journal of Solid-State Circuits, 37(10), 1335–1338.CrossRefGoogle Scholar
  32. 32.
    Thomas, K. P. J., Rana, R. S., & Lian, Y. (2005). A 1 GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion. In Proceedings of IEEE Asia and South Pacific design automation conference (ASP-DAC) (pp. 665–670).Google Scholar
  33. 33.
    Choe, M.-J., Baek, K.-H., & Teshome, M. (2005). A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation. IEEE Journal of Solid-State Circuits, 40(12), 2456–2468.CrossRefGoogle Scholar
  34. 34.
    Huang, Q., Francese, P. A. Martelli, C. & Nielsen, J. (2004). A 200 MS/s 14 b 97 mW DAC in 0.18 μm CMOS. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 364–365).Google Scholar
  35. 35.
    Chen, T., & Gielen, G. G. E. (2006). The analysis and improvement of a current-steering DACs dynamic SFDR-I: The cell-dependent delay differences. IEEE Transactions on Circuits Systems I: Regular Papers, 53(1), 3–15.CrossRefGoogle Scholar
  36. 36.
    Shui, T., Schreier, R., & Hudson, F. (1999). Mismatch shaping for a current-mode multibit delta-sigma DAC. IEEE Journal of Solid-State Circuits, 34(3), 331–338.CrossRefGoogle Scholar
  37. 37.
    Schofield, W., Mercer, D., & Onge, L. S. (2003). A 16 b 400 MS/s DAC with < − 80 dBc IMD to 300 MHz and < − 160 dBm/Hz noise power spectral density. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 126–127).Google Scholar
  38. 38.
    Tseng, W.-H., Fan, C.-W., & Wu, J.-T. (2011). A 12-bit 1.25-GS/s DAC in 90 nm CMOS with > 70 dB SFDR up to 500 MHz. IEEE Journal of Solid-State Circuits, 46(12), 2845–2856.CrossRefGoogle Scholar
  39. 39.
    Olieman, E., Annema, A., & Nauta, A. (2014). A 110 mW, 0.04 mm2, 11 GS/s 9-bit interleaved DAC in 28 nm FDSOI with > 50 dB SFDR across Nyquist. In IEEE symposium on VLSI circuits digest of technical papers (pp. 1–2).Google Scholar
  40. 40.
    Galton, I., & Carbone, P. (1995). A rigorous error analysis of D/A conversion with dynamic element matching. IEEE Transactions on Circuits Systems II: Analog and Digital Signal Processing, 42(12), 763–772.CrossRefGoogle Scholar
  41. 41.
    Soares, C. F. T., & Petraglia, A. (2015). Automatic placement to improve capacitance matching using a generalized common-centroid layout and spatial correlation optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(10), 1691–1695.CrossRefGoogle Scholar
  42. 42.
    Lin, W.-T., & Kuo, T.-H. (2012). A compact dynamic-performance-improved current-steering DAC with random rotation-based binary-weighted selection. IEEE Journal of Solid-State Circuits, 47(2), 444–453.CrossRefGoogle Scholar
  43. 43.
    Lin, C.-H., et al. (2009). A 12 b 2.9 GS/s DAC with IM3 < − 60 dBc Beyond 1 GHz in 65 nm CMOS. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 74–75).Google Scholar
  44. 44.
    Su, S., & Chen, M. S.-W. (2016). A 12-bit 2 GS/s dual-rate hybrid DAC with pulse-error pre-distortion and in-band noise cancellation achieving > 74 dBc SFDR and < − 80 dBc IM3 up to 1 GHz in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 51(12), 2963–2978.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Longqiang Lai
    • 1
  • Xueqing Li
    • 1
  • Jianan Liu
    • 2
  • Huazhong Yang
    • 1
  1. 1.Department of Electronics EngineeringTsinghua UniversityBeijingChina
  2. 2.Xiaomi Inc.BeijingChina

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