A 14bit 500MS/s DAC with 211MHz 70 dB SFDR bandwidth using TRIDEMRZ
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Abstract
Timerelaxed interleaving dynamic element matching returntozero (TRIDEMRZ) is proposed and verified in this paper to improve the spuriousfree dynamic range (SFDR) of currentsteering digitaltoanalog converters (DACs). It incorporates timerelaxed interleaving (TRI), returntozero, and the dynamicelementmatching techniques, in a way that fosters the strength of each technique. As analyzed in this paper, merits beyond the combination of these techniques could be achieved. Firstly, TRIDEMRZ provides a new dimension in the space domain, rather than the time domain, to explore the methods of mitigating nonlinear switching distortions. Secondly, this paper proves that, the image tone caused by typical channel mismatches between interleaved subDACs can be randomized into noise with TRIDEMRZ. Circuit simulations and analysis are provided. An experimental 14bit 500MS/s currentsteering DAC in 65 nm CMOS has been fabricated and measured, showing 81 dB SFDR at 5.5 MHz and more than 70 dB SFDR up to 211 MHz bandwidth. The SFDR improvement achieved by TRIDEMRZ is more than 10 dB, which further verifies the effectiveness of TRIDEMRZ.
Keywords
Digitaltoanalog converter (DAC) Dynamic element matching (DEM) Channel mismatch Timerelaxed interleaving Currentsteering1 Introduction
While most highspeed digitaltoanalog converters (DACs) are implemented in the currentsteering topology because of the high intrinsic switching speed and moderate matching property, recent research has revealed two main bottlenecks towards a high dynamic range [1, 2, 3, 4]. One is the current source mismatch that affects the output amplitude. The other one is the nonlinear distortion caused by codedependent switching glitches, which becomes more severe at a higher frequency with inevitable switching time mismatch and more switching activities.
Among various approaches, dynamic element matching (DEM) and returntozero (RZ) techniques are widely used to mitigate the aforementioned two aspects [1, 2, 4, 5]. With sufficient randomization, DEM is effective in averaging out current source mismatches. Meanwhile, RZ techniques are effective in mitigating the intersymbolinterference (ISI) to reduce the codedependent switching distortions. In [2], dynamic element matching returntozero (DMRZ) combined DEM and halfacycle RZ, leading to the first CMOS DAC with 70 dB SFDR up to 800 MHz.

The proposed TRIDEMRZ reveals and confirms a new design dimension by trading space (associated area and power) for better dynamic performance with assisting digital signal processing techniques such as randomization. Note that, in our proposed TRIDEMRZ, switching distortions in the final output are reduced by means of space domain randomization, which is fundamentally different from the previous DMRZ method that deals with switching distortions in the time domain, which will be analyzed in Sect. 2. Such a new dimension provides more chance of distortion suppression and performance enhancement.

The combination of interleaving and DEM, not only randomizes the static mismatch of current sources inside each subDAC, but also randomizes the channel mismatch between the two subDACs. In this paper, we theoretically prove that under certain mismatch distribution, the channel mismatch between interleaved subDACs can be randomized, and the related image tone can be smashed into noise with TRIDEMRZ. In this way, TRIDEMRZ provides a new method to deal with the channel mismatch in interleaving.
The rest of this paper is organized as follows. Section “Static mismatches and switching distortions” revisits the existing study of current source mismatches and codedependent switching glitches revealing the new design dimension of TRIDEMRZ. The derivation and analysis of channel mismatch randomization using TRIDEMRZ are provided in Section “Channel mismatch randomization”. The implementation and measurement of the experimental DAC are provided in Section “Implementation and experiment”. Finally, Section “Conclusion” concludes this paper.
2 Static mismatches and switching distortions
This section revisits the inherent features of the current source mismatches and codedependent switching glitches, so as to get indepth understanding of the pros and cons of existing solutions. This also shows how DEM and RZ techniques could potentially outperform or collaborate with other techniques. Then the basic concept of TRIDEMRZ technique is revisited to show how it expands the design space for a higher dynamic range.
2.1 Problems in dealing with inter subDACs current source mismatches
Various sources result in systematic and random mismatches between current sources in fabricated currentsteering DACs. These mismatches not only limit the static output signal amplitude, but also deteriorate the spectral performance [1, 2, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]. DEM is a method to deal with the mismatches by selecting current sources dynamically from random places in the current source array to make the integrated amplitude errors less codedependent [1, 2]. Such randomization leads to averaging of the mismatches, and also contributes to harmonic distortion suppression. As the effectiveness of existing DEM on the mismatch noise shaping depends on “averaging over time” [2, 20], signals with amplitude near full scale at a higher frequency have less room for randomization and consequently, less mismatch averaging benefits in wideband Nyquist DACs. Nevertheless, for applications where SFDR is the bottleneck due to the current source mismatches, DEM is intriguing to improve SFDR by turning distortions into flat noise [1].
Meanwhile, there is urgent need of a good method to deal with the channel mismatch between the subDACs. Such channel mismatches exist when an interleaving DAC has more than one subDACs, as in [3, 4]. Section 2.3 of this paper will introduce the proposed interleaving DEM method for such DACs.
2.2 Problems in dealing with switching glitch distortions
Nevertheless, it is important to understand that even if the ISI effects (history effects) are removed, some harmonics induced by the inputcodedependent effects mentioned above could not be fully eliminated. For example, the switching or resampling timing skews [35], the resampling coupling glitches or switch coupling glitches, as well as the charge resettling at the internal nodes inside each current route due to switching or resampling, will cause codedependent glitches with carryon harmonics at the DAC output. Therefore, these approaches to a high dynamic range, either by optimizing the existing circuit, layout, segmentation, adding dummy switching activities, or employing RZ operations, are useful, but still have inherent limitations for a DAC with a high SFDR.
2.3 Proposed TRIDEMRZ in comparison with DEM and interleaving techniques
The problems of existing incorporated DEM and RZ methods, as revealed in [3], are highspeed design challenges or drawbacks, including (1) tight timing requirement as the switching activities need to settle within half a clock period, and (2) signal energy loss, and higher image tones in the 2nd Nyquist zone to filter out due to the RZ output pattern. The mitigating method is timerelaxed interleaving (TRI) [3], which uses two parallel interleaving subDACs, each operating in a mode of alternate NRZ and RZ that settles within one full clock period instead of half a clock period. Figure 3 shows the TRIDRRZ waveforms. It is clear that the two DRRZ problems are solved. The SFDR can also be higher because the signal power is higher than DRRZ while the total number of switching activities remains the same.
The technique of TRI in [3] is a new concept to seek for higher performance by trading extra space or area while doing random switching, which is fundamentally different from the previous DRRZ or DMRZ method of doing it in the time domain. The performance improvement would be significant when timing and amplitude mismatches caused by the increased area are not yet the performance bottleneck. Unfortunately, the previously proposed technique of TRIDRRZ in [3] did not make full use of TRI to deal with current source mismatches in each subDAC, or between subDACs. This is because subDACs in [3] are (1) physically and operationally independent of each other, and (2) thermometerdecoded without DEM as depicted in Fig. 3(b).
Same as the evolvement from DRRZ to TRIDRRZ, the proposed TRIDEMRZ has essential advantages over DMRZ, including (1) the relaxation of settlingtime requirements, (2) the increase of signal energy and more suppression of image tones, and (3) higher SFDR due to higher signal power but the same total number of randomized switching activities and corresponding switching glitches.
It is noted that the total number of switching activities in TRIDEMRZ is the same as DMRZ, DRRZ, and TRIDRRZ, all higher than NRZ. Detailed analysis in this aspect has been provided in [3]. Such behavior results in higher noise level than NRZ DACs, which is one side effect of these techniques. Another side effect of TRIDEMRZ is the doubled number of current sources, which is the main drawback of interleaving techniques. However, compared with the traditional uncalibrated interleaved DACs, e.g. the DAC with TRIDRRZ in [3], the area of each subDACs could be smaller with TRIDEMRZ. This is because the dynamic element matching in TRIDEMRZ transforms the mismatchcaused harmonics or tones into noise with lower requirement on the area for current source matching [13].
Comparisons between TRIDEMRZ and others with NRZ as the baseline
Specifications  NRZ  DRRZ  DMRZ  TRIDRRZ  TRIDEMRZ 

Settling requirement  –  –  –  
Output signal power  –  –  –  
Image suppression^{a}  –  –  –  
Switch driving power  –  
Static mismatch averaging  –  ☺  ☺  
Chip area  –  –  ☺  
SFDR^{b}  –  ☺  ☺☺  ☺☺  ☺☺☺ 
3 Channel mismatch randomization
This section reveals and studies the channel mismatch randomization property of TRIDEMRZ. The use of DEM allows each subDACs to be smaller size, which on the contrary deteriorates the channel mismatch for interleaving technique. Fortunately, the use of DEM not only randomizes the static mismatch inside each subDAC but also randomizes the channel mismatch between two subDACs at the same time. Since DEM introduces redundant combination of current sources, the use of DEM equivalently improves the alternative selection for subDACs compared with the interleaving without DEM [39]. This property can help to obscure the channel mismatch between the two subDACs. The detailed derivation and analyses of this feature are provided in this section.
3.1 Mathematical model
Based on the DEM analysis for one single channel DAC, the rest of this subsection provides the analysis of channel mismatch randomization incorporating DEM and interleaving.
3.2 Numerical simulation
For example, the 11th sample in Fig. 5 has normalized arithmetic sum deviation near 2LSB while the quadratic sum deviation is around 10LSB^{2} and for the 4th sample, they are near zero LSB and 10LSB^{2} separately.
In summary, TRIDEMRZ incorporating DEM and interleaving not only improves the linearity of each subDACs, but also suppresses the image tone caused by channel mismatch in interleaving. Besides, the simulation above emphasizes the importance of (13a) in the design of DAC using TRIDEMRZ.
4 Implementation and experiment
This section provides the implementation of TRIDEMRZ and the experimental results of the fabricated experimental DAC.
4.1 Chip implementation
A linear feedback shift register (LFSR) is used as PRNG, and a random rotationbased binaryweighted selection (RRBS) scheme in [42] is employed for the DEM decoder.
For the subDAC which returns to zero, the PRNG randomly selects 32 MSB current sources and 15 ULSB current sources to the DAC’s positive output port and the remaining current sources in MSB and ULSB to the negative output port. Through this way, the differential output of this sub DAC is almost zero with a DC offset of only one LSB which has very little impact on the dynamic performance and is negligible in most applications because this DC offset is isolated by the transformer used for AC differentialtosingle conversion [3].
4.2 Measurement results
Measured performance of the proposed TRIDEMRZ DAC
Technology  CMOS 65 nm 
Resolution  14 bits 
Clock rate  500MS/s 
SFDR  > 70 dB within 211 MHz 
INL  + 5/− 7 LSB 
Supply voltage  1.2 V/2.5 V 
Power consumption  106 mW 
Active area  0.42 mm^{2} 
Comparisons with stateoftheart works
Specifications  This work  [38]  [2]  [3]  [44] 

JSSC2011  ISSCC2013  TCASI2014  JSSC2016  
Technique  TRIDEMRZ  DRRZ  DMRZ  TRIDRRZ  HybridDAC 
Process (nm)  65  90  40  130  65 
Core area (mm^{2})  0.42  0.825  0.016  1.20  0.57 
Supply (V)  1.2/2.5  1.2/2.5  1.2  1.2/2.5  1/2.5 
DAC power (mW)  106  128  40  299  681 
Sampling rate (GS/s)  0.25/0.5  1.25  1.6  0.50  2 
Resolution (bits)  14  12  12  14  12 
Calibration  No  Yes  No  No  Yes 
Fullscale current (mA)  32  16  16  16  16 
SFDR_{LF} (dB)  90.0^{b}  75  74  84.8  98 
SFDR_{fs/2} (dB)  79.2^{b}  66  70.3  73.5  74.4 
FOM (10^{4}Hz/mW)^{a}  47^{b}  7.4  46  9.2  83.3 
5 Conclusion
This paper has revealed that, other than simply incorporating DMRZ and timerelaxed interleaving, TRIDEMRZ shows more merits. In addition to mitigating the nonlinear distortions caused by codedependent switching activities, TRIDEMRZ provides an effective method to deal with the channel mismatch in interleaving architectures. The exploration of TRIDEMRZ has significantly extended the design space of wideband highSFDR DACs by trading additional randomized switch activities and chip area for a higher SFDR. In addition to the theoretical analysis, a 14bit 500MS/s currentsteering DAC in 65 nm is implemented. The measured SFDR improvement further verifies the effectiveness of TRIDEMRZ.
Notes
Acknowledgements
This work was supported in part by the National High Technology Research and Development Program of China (No. 2013AA014103) and in part by the NSFC under Grant #61720106013 and #61532017.
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