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A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability


Conventional structure of delay locked loops (DLLs) is modified to achieve better jitter and smaller lock time. In the proposed structure, analog charge pump is eliminated, to remove the problems of leakage current on output capacitance, and is replaced by combination of a digital accumulator (ACC) and a digital-to-analog converter. A programmable ACC is also proposed, to dynamically control the loop gain and lock time. When the loop enters to lock region at the first time, a lock detector block disables ACC and equivalent digital code is stored on a latch array. So, a fixed control voltage controls delay elements and the systematic jitter, due to periodic discharge of control voltage. RMS jitter of less than 33.5 and 1.6 ps are achieved at 20 and 625 MHz operating frequencies, respectively, when the supply is subject to 110 mV random noise and also 40 mV periodic noise, related to generated clock signals. Lock time is reduced from 38 to 2 µs at 20 MHz, and also from 900 to 45 ns at 600 MHz, when the proposed dynamic control mechanism is applied on the loop. Total power consumption for the main core of DLL is 7.85 mW at 1.8 V supply in 0.18 µm CMOS process.

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Correspondence to Sarang Kazeminia Ph.D..

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Kazeminia, S., Abdollahi, R. & Hejazi, A. A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability. Analog Integr Circ Sig Process 94, 507–517 (2018).

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  • Delay locked loop
  • Low jitter DLL
  • Dynamic gain control
  • DLL lock time
  • DLL loop gain