Design considerations of CMOS active inductor for low power applications

  • Jack Ou
  • Pietro M. Ferreira


Previous studies have shown that \(g_m/I_D\) (transconductance-to-drain-current) ratio based design is useful for optimizing analog circuits. In this paper, we explore challenges associated with designing a low-power active inductor. We focus in particular on sizing issues that arise as the transistor speed is maximized and the current consumption is minimized. Finally, we apply the results to design an amplifier integrated with an active inductor in \(0.18\,\upmu \hbox{m}\) CMOS process and show that by systematically working through sizing issues, a \(10\,\upmu \hbox{A}\) sub GHz amplifier can be designed.


Active inductor \(g_m/I_D\) design Gyrator-C active inductor 


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© Springer Science+Business Media, LLC 2017

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringCalifornia State University NorthridgeNorthridgeUSA
  2. 2.GeePs (UMR CNRS 8507), CentraleSuplecUniversité Paris-SaclayGif-sur-YvetteFrance

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