A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs
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This paper presents a novel high performance, ultra-low power scalable CMOS charge pump (CP) design for analog phase-locked loops (PLLs) fabricated in all-digital nanoscale IC processes. The compact CP circuit uses four minimally-sized transistor switches and a relatively small capacitor for transferring charge within the PLL to adjust the voltage controlled oscillator frequency in the PLL control loop. Unlike the state of the art designs, the proposed CP topology does not use current mirrors, nor does it suffer from traditional mismatch errors due to its unique structure. Additionally, this charge transfer-based CP has the ability to operate at very low supply voltages well below 1 V. The fast switching action of the proposed CP allows for the use of a no-added delay D-flip flop-based phase-frequency detector resulting in a reduced PLL control loop delay and very low reference spurs in the overall PLL design. The proposed CP has been placed in a 0.5–10 GHz PLL, fabricated, and physically tested in an all-digital 40 nm TSMC CMOS process. Additionally, post-silicon measurements of the CP circuit have been completed with a variable 0.2–1.2 V supply and a 50 MHz–1 GHz reference frequency. The proposed CP has an active area of 0.0004 mm2, consumes on average 250 pW power, and has a 0.1°–0.3° phase error, dependent on the PLL frequency of operation.
KeywordsCharge pump Phase-locked loop PLL Frequency synthesis Ultra-low power analog ICs Low supply voltage Charge transfer Nanoscale CMOS
The authors would like to thank F. Maloberti, M. Pardo, M. Chen, E. Maby, E. Pakbaznia, and R. Schober for their comments and valuable suggestions. This work was supported in part by MOSIS, DARPA, and NSF.
- 1.Rhee, W. (1999, July). Design of high-performance CMOS charge pumps in phase-locked loops. In Circuits and Systems, 1999. ISCAS’99. Proceedings of the 1999 IEEE International Symposium on (Vol. 2, pp. 545–548). IEEE.Google Scholar
- 3.Shi, X., Imfeld, K., Tanner, S., Ansorge, M., & Farine, P. A. (2006). A low-jitter and low-power CMOS PLL for clock multiplication. In Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European (pp. 174–177). IEEE.Google Scholar
- 4.Charles, C. T., & Allstot, D. J. (2008, May). A buffered charge pump with zero charge sharing. In 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. Seattle, WA.Google Scholar
- 6.Rategh, H. R., & Lee, T. H. (2007). Multi-GHz frequency synthesis & division: frequency synthesizer design for 5 GHz wireless LAN systems. Berlin: Springer Science & Business Media.Google Scholar
- 7.Keliu, S., & Sánchez-Sinencio, E. (2006). CMOS PLL synthesizers: analysis and design (Vol. 783). Berlin: Springer Science & Business Media.Google Scholar
- 9.Thompson, M. (2006). Intuitive analog circuit design. oxford: Newnes.Google Scholar
- 10.Schober, S., & Choma, J. (2015). A dual reset D flip-flop phase-frequency detector for phase locked loops. In Proceedings of the XXI Iberchip Workshop (IWS-2015), Montevideo, Uruguay (pp. 1–4).Google Scholar
- 12.Schober, S., & Choma, J. (2015). A 1.25 mW 0.8–28.2 GHz charge pump PLL with 0.82 ps RMS jitter in all-digital 40 nm CMOS. In Circuits and Systems (ISCAS), 2015 IEEE International Symposium on (pp. 549–552). IEEE.Google Scholar
- 13.Fischette,DM., Loke, A. L. S., Oshima, M. M., Doyle, B. A., Bakalski, R., DeSantis, R. J., Thiruvengadam A, Wang C. L, Talbot G. R., Fang, E. S. (2010, February). A 45 nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. In 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (pp. 246–247). IEEE.Google Scholar
- 16.Deng, W., Yang, D., Ueno, T., Siriburanon, T., Kondo, S., Okada, K., & Matsuzawa, A. (2014, February). 15.1 A 0.0066 mm 2 780 μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International(pp. 266-267). IEEE.Google Scholar
- 17.Sai, A., Kobayashi, Y., Saigusa, S., Watanabe, O., & Itakura, T. (2012, February). A digitally stabilized type-III PLL using ring VCO with 1.01 ps rms integrated jitter in 65 nm CMOS. In 2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (pp. 248–250). IEEE.Google Scholar