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A CMOS EEG detection system with a configurable analog front-end architecture

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Abstract

This paper proposes a configurable analog front-end (AFE) chain architecture used in the EEG detection system. The proposed chain consists of three stages: the first and the third stages are instrumentation amplifier and programmable gain amplifier, respectively, and the second stage is notch filter with low pass feature. The proposed architecture relaxes the design of the notch filter and the analog-to-digital converter (ADC) used in building the EEG detection system. A basic building block is the digitally programmable balanced output operational transconductance amplifier (DPOTA), which is proposed to realize the AFE blocks. A successive-approximation ADC (SA-ADC) architecture is mostly designed on digital circuits in order to lower the power dissipation. Based on this, PSpice post layout simulation results for the overall EEG detection system using 0.25-µm CMOS technology are also given. The overall configurable gain/filtering chain architecture has a total gain ranging from 61 to 84 dB, a total power dissipation of 32 µW and input referred noise spectral density of 4 µV/ \(\sqrt {\text{Hz}}\).

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Authors and Affiliations

  1. Electrical Computer Engineering Department, University of Sharjah, Sharjah, UAE

    Aisha A. Alhammadi, Tasnim B. Nazzal & Soliman A. Mahmoud

  2. Electrical Engineering Department, Fayoum University Egypt, Faiyum, Egypt

    Soliman A. Mahmoud

Authors
  1. Aisha A. Alhammadi
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  2. Tasnim B. Nazzal
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  3. Soliman A. Mahmoud
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Correspondence to Soliman A. Mahmoud.

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Alhammadi, A.A., Nazzal, T.B. & Mahmoud, S.A. A CMOS EEG detection system with a configurable analog front-end architecture. Analog Integr Circ Sig Process 89, 151–176 (2016). https://doi.org/10.1007/s10470-016-0826-x

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  • DOI: https://doi.org/10.1007/s10470-016-0826-x

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