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A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications

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Abstract

A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO) and digital ΣΔ quantization noise cancellation based least mean square (LMS) algorithm, the DPLL achieves -110dBc/Hz and -140dBc/Hz for in-band and 10 MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz and 1 MHz bandwidth. The digital PLL is simulated in a 65 nm CMOS process, consuming 11.2 mW from a 1.0 V supply.

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Notes

  1. In ring Vernier TDCs, the taps differ by integer times of ring stage number..

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Acknowledgments

The authors are deeply grateful to ST Microelectronics for the generous silicon donation. This work was supported by the Swedish Foundation for Strategic Research (SSF) under the DARE project.

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  1. Ping Lu

    Present address: Silicon Labs, Austin, TX, USA

Authors and Affiliations

  1. Lund University, Lund, Sweden

    Ahmed Mahmoud, Pietro Andreani & Ping Lu

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  1. Ahmed Mahmoud
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  2. Pietro Andreani
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  3. Ping Lu
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Correspondence to Ahmed Mahmoud.

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Mahmoud, A., Andreani, P. & Lu, P. A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications. Analog Integr Circ Sig Process 89, 337–345 (2016). https://doi.org/10.1007/s10470-016-0786-1

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