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OTA-C based high-speed analog processing for real-time fault location in electrical power networks

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Abstract

This paper explores the potential and limitations of analog integrated circuit techniques for the simulation of low-loss or lossless 1D or 2D transmission mediums. In this approach, a transmission line is mapped into a ladder consisting of N identical LC elements, each modeling a finite length increment of the line. Inductors are then emulated by a gyrator-capacitor combination, yielding a classical transconductor-capacitor (gm-C) circuit, suitable for integration. The validity of this approximation is discussed in the context of fault location in power networks, an application based on the electromagnetic time-reversal method. Design constraints on gm-C circuits are derived and non-ideal effects such as finite open-loop gain and component mismatches are evaluated. It is shown that a simple analog implementation can locate the fault within 1 % accuracy with a significant speed advantage over classical computational methods, reducing the processing time to <100 ms.

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Acknowledgments

This research has been funded by the Swiss National Science Foundation (SNSF), within the Project N: 146414.

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Authors and Affiliations

  1. Electronics Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland

    François Gaugaz, François Krummenacher & Maher Kayal

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  1. François Gaugaz
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  2. François Krummenacher
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  3. Maher Kayal
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Correspondence to François Gaugaz.

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Gaugaz, F., Krummenacher, F. & Kayal, M. OTA-C based high-speed analog processing for real-time fault location in electrical power networks. Analog Integr Circ Sig Process 89, 61–67 (2016). https://doi.org/10.1007/s10470-016-0742-0

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  • DOI: https://doi.org/10.1007/s10470-016-0742-0

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