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RF channelizer architectures using 3-way iterative down conversion for concurrent or fast-switching spectrum analysis

  • Karthik Tripurari
  • Linxiao Zhang
  • Yang Xu
  • David Gidony
  • Branislav Jovanovic
  • Harish Krishnaswamy
  • Peter Kinget
Article

Abstract

A wide-band RF channelizer architecture using the concept of 3-way iterative down-conversion is introduced. An example RF channelizer implementation splits the input spectrum of 0.6–9 GHz into 7 channels each with a 1.2 GHz bandwidth. This RF channelizer implementation has the ability of concurrently down-converting 3 channels enabling multi-Gbps aggregate data reception. It further demonstrates the ability to rapidly switch from receiving one channel to another which is crucial for rapid spectrum analysis. A prototype of the RF channelizer has been fabricated in a 65 nm standard CMOS process. A 400 Mbps (BPSK) data reception has been demonstrated by down-converting two channels concurrently. Channel switching can be as fast as 8 ns and is always faster than \(1\,\upmu s\). The chip occupies an area of 2 mm \(\times\) 1 mm and consumes an average power of 435 mW while offering a dynamic range between 58 and 63 dB.

Keywords

RF channelizer architecture Iterative down-conversion Concurrent receiver Rapid channel switching Spectrum analysis 

Notes

Acknowledgments

We thank Prof. R. Gharpurey (U. of Texas, Austin) for technical discussions and Integrand Software and Mentor Graphics for granting us licenses for the EMX and AFS CAD tools respectively. This research was supported by NSF under grant 1002064 and by AFRL under the DARPA CLASIC program (agreement FA8650-11-1-7159). The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of NSF, AFRL and DARPA, or the U.S. Government.

References

  1. 1.
    Goel, A., Analui, B., & Hashemi, H. (2012). A 130-nm CMOS 100-Hz–6-GHz reconfigurable vector signal analyzer and software-defined receiver. IEEE Transactions on Microwave Theory and Techniques, 60(5), 1375–1389.CrossRefGoogle Scholar
  2. 2.
    Wang, Y.-J. (2009). Circuits and systems for wireless concurrent communication. Ph.D. dissertation, California Institute of Technology.Google Scholar
  3. 3.
    Mandal, S., Zhak, S., & Sarpeshkar, R. (2009). A bio-inspired active radio-frequency silicon cochlea. IEEE Journal of Solid-State Circuits, 44(6), 1814–1828.CrossRefGoogle Scholar
  4. 4.
    Gharpurey, R., & Kinget, P. (2009) .Channelized front ends for broadband analog and RF signal processing with merged LO synthesis. In IEEE Dallas circuits and systems workshop (DCAS) (pp. 1–4).Google Scholar
  5. 5.
    Hsieh, T.-L., Kinget, P., & Gharpurey, R. (2008). A rapid interference detector for ultra wideband radio systems in 0.13um CMOS. In IEEE radio frequency integrated circuits symposium (pp. 347–350).Google Scholar
  6. 6.
    Krishnaswamy, H., Tripurari, K., Xu, Y., Zhang, L., Gidony, D., Jovanovic, B., & Kinget, P. (2014). RF channelizer architectures using iterative downconversion for concurrent or fast-switching spectrum analysis. In IEEE 57th international Midwest symposium on circuits and systems (MWSCAS) (pp. 977–980).Google Scholar
  7. 7.
    Razavi, B. (2004). A study of injection locking and pulling in oscillators. IEEE Journal of Solid-State Circuits, 39(9), 1415–1424.CrossRefGoogle Scholar
  8. 8.
    Weldon, J., Narayanaswami, R., Rudell, J., Lin, L., Otsuka, M., Dedieu, S., et al. (2001). A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers. IEEE Journal of Solid-State Circuits, 36(12), 2003–2015.CrossRefGoogle Scholar
  9. 9.
    Razavi, B. (1997). Design considerations for direct-conversion receivers. IEEE Transactions on Circuits and Systems II, 44(6), 428–435.CrossRefGoogle Scholar
  10. 10.
    Elmala, M., & Embabi, S. (2004). Calibration of phase and gain mismatches in Weaver image-reject receiver. IEEE Journal of Solid-State Circuits, 39(2), 283–289.CrossRefGoogle Scholar
  11. 11.
    Ru, Z., Klumperink, E., Wienk, G., & Nauta, B. (2009). A software-defined radio receiver architecture robust to out-of-band interference. In Digest of technical papers IEEE international solid-state circuits conference (ISSCC) (pp. 230–231,231a).Google Scholar
  12. 12.
    Forbes, T. (2013). Circuit techniques for programmable broadband radio receivers (chapter 4). Ph.D. dissertation, University of Texas, Austin.Google Scholar
  13. 13.
    Glas, J. (1998). Digital I/Q imbalance compensation in a low-IF receiver. IEEE Global Telecommunications Conference (GLOBECOM), 3, 1461–1466.Google Scholar
  14. 14.
    Zhang, L., Xu, Y., Tripurari, K., Kinget, P., & Krishnaswamy, H. (2015). Analysis and design of a 0.6- to 10.5-GHz LNTA for wideband receivers. IEEE Transactions on Circuits and Systems II, 62(5), 431–435.CrossRefGoogle Scholar
  15. 15.
    Rafi, A., Piovaccari, A.,Vancorenland, P., & Tuttle, T. (2011). A harmonic rejection mixer robust to RF device mismatches. In Digest of technical papers IEEE international solid-state circuits conference (ISSCC) (pp. 66–68).Google Scholar
  16. 16.
    Cha, H.-K., Song, S.-S., Kim, H.-T., & Lee, K. (2008). A CMOS harmonic rejection mixer with mismatch calibration circuitry for digital TV tuner applications. IEEE Microwave and Wireless Components Letters, 18(9), 617–619.CrossRefGoogle Scholar
  17. 17.
    Bagheri, R., Mirzaei, A., Chehrazi, S., Heidari, M., Lee, M., Mikhemar, M., et al. (2006). An 800-MHz–6-GHz software-defined wireless receiver in 90-nm CMOS. IEEE Journal of Solid-State Circuits, 41(12), 2860–2876.CrossRefGoogle Scholar
  18. 18.
    Yang, T.,Tripurari, K., Krishnaswamy, H., & Kinget, P. (2013). A 0.5GHz–1.5GHz order scalable harmonic rejection mixer. In 2013 IEEE Radio frequency integrated circuits symposium (RFIC) (pp. 411–414).Google Scholar
  19. 19.
    Zverev, A. (1967). Handbook for filter synthesis. New York: Wiley.Google Scholar
  20. 20.
    Heydari, P., & Mohavavelu, R. (2003). Design of ultra high-speed CMOS CML buffers and latches. In Proceedings of IEEE international symposium on circuits and systems (ISCAS) (Vol. 2, pp. II–208).Google Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  • Karthik Tripurari
    • 1
  • Linxiao Zhang
    • 1
  • Yang Xu
    • 1
  • David Gidony
    • 1
  • Branislav Jovanovic
    • 1
  • Harish Krishnaswamy
    • 1
  • Peter Kinget
    • 1
  1. 1.Department of Electrical EngineeringColumbia UniversityNew YorkUSA

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