RF channelizer architectures using 3-way iterative down conversion for concurrent or fast-switching spectrum analysis
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A wide-band RF channelizer architecture using the concept of 3-way iterative down-conversion is introduced. An example RF channelizer implementation splits the input spectrum of 0.6–9 GHz into 7 channels each with a 1.2 GHz bandwidth. This RF channelizer implementation has the ability of concurrently down-converting 3 channels enabling multi-Gbps aggregate data reception. It further demonstrates the ability to rapidly switch from receiving one channel to another which is crucial for rapid spectrum analysis. A prototype of the RF channelizer has been fabricated in a 65 nm standard CMOS process. A 400 Mbps (BPSK) data reception has been demonstrated by down-converting two channels concurrently. Channel switching can be as fast as 8 ns and is always faster than \(1\,\upmu s\). The chip occupies an area of 2 mm \(\times\) 1 mm and consumes an average power of 435 mW while offering a dynamic range between 58 and 63 dB.
KeywordsRF channelizer architecture Iterative down-conversion Concurrent receiver Rapid channel switching Spectrum analysis
We thank Prof. R. Gharpurey (U. of Texas, Austin) for technical discussions and Integrand Software and Mentor Graphics for granting us licenses for the EMX and AFS CAD tools respectively. This research was supported by NSF under grant 1002064 and by AFRL under the DARPA CLASIC program (agreement FA8650-11-1-7159). The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of NSF, AFRL and DARPA, or the U.S. Government.
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