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A 67.2 dB SNDR 1.8-V 12-bit 2-MS/s SAR ADC without calibration

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Abstract

This paper presents a 12-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) without calibration based on 0.18 μm 1P6M CMOS technology. To gain one bit of resolution without increasing the number of capacitors, one-side-fixed technique is used to generate the proposed switching procedure based on merged capacitor switching (MCS) switching procedure. Besides, a new DAC control logic is proposed by inserting the SAR logic circuits into level-shift circuits to reduce the complexity of the DAC control logic, enable high-speed and low-power operation and reduce the chance of race and hazard of the combinational logic circuit at the same time. The measured results show the proposed ADC achieves an SNDR of 67.26 dB and consumes 183.3 μW at 1.8 V power supply and 2 MS/s, the peak DNL and INL are +0.66/−0.64 LSB and +0.75/−0.74 LSB, respectively, resulting in a figure-of-merit of 48.63 fJ/conversion-step. The ADC core occupies an active area of 630 × 570 µm2.

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Acknowledgments

This work was supported by the National Natural Science Foundation of China (61234002, 61322405, 61306044 and 61376033), the National High-tech Program of China (2013AA014103).

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Authors and Affiliations

  1. School of Microelectronics, Xidian University, Xi’an, 710071, People’s Republic of China

    Maliang Liu, Yi Xie & Zhangming Zhu

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  1. Maliang Liu
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  2. Yi Xie
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  3. Zhangming Zhu
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Correspondence to Zhangming Zhu.

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Liu, M., Xie, Y. & Zhu, Z. A 67.2 dB SNDR 1.8-V 12-bit 2-MS/s SAR ADC without calibration. Analog Integr Circ Sig Process 86, 151–158 (2016). https://doi.org/10.1007/s10470-015-0662-4

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  • DOI: https://doi.org/10.1007/s10470-015-0662-4

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