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A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology


A 6-Gbps dual-mode digital clock and data recovery (CDR) circuit for both the mesochronous clocking system and the plesiochronous clocking system has been developed. Fabricated in a 65-nm CMOS technology, the prototype consumes 25.2 and 22.8-mW from 1.2-V supply and root-mean-square jitter of the recovered clock was measured to be 7.2 and 8.5-ps for 6-Gbps mesochronous system and plesiochronous system, respectively. For both operation modes, less than 10−12 bit-error-rate was achieved with 27-1 pseudo-random binary sequence pattern and active area of the implemented CDR circuit is 0.025-mm2.

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This work was supported by the IT R&D program of MOTIE (Ministry of Trade, Industry and Energy) and KEIT (Korea Evaluation Institute of Industrial Technology) (No. 10044451, 4K UHD Level AV Signal Transmit SoC for Mobile Device) and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2013R1A2A2A01004958). The CAD tools were provided by IC Design Education Center (IDEC), Korea.

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Correspondence to Changsik Yoo.

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Jeon, MK., Yoo, C. A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology. Analog Integr Circ Sig Process 85, 209–215 (2015).

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  • Clock and data recovery (CDR)
  • Phase locked loop (PLL)
  • Digitally-controlled oscillator (DCO)