Distributed LDO regulators in a 28 nm power delivery system

  • Inna Vaisband
  • Burt Price
  • Selçuk Köse
  • Yesh Kolla
  • Eby G. Friedman
  • Jeff Fischer


A fully integrated power delivery system with distributed on-chip low-dropout (LDO) regulators developed for voltage regulation in portable devices and fabricated in a 28 nm CMOS process is described. Each LDO employs adaptive bias for fast and power efficient voltage regulation, exhibiting 64 ps response time of the regulation loop and 99.49 % current efficiency. An adaptive compensation network is also employed within the distributed power delivery system to maintain a stable system response within 25 to 105 °C and 10 % voltage variations with a capacitive load of more than 472 pF. No off-chip capacitors are required. Under a 788 mA load current step with 5 ns load edge, the power delivery system exhibits less than 15 % voltage droop for nominal input and output voltages, and a minimum dropout of 0.1 V. Each of the LDO regulators with the adaptive networks and bias current generator occupies 85 μm × 42 μm in a 28 nm CMOS process. All of the test measurements are performed in a distributed power delivery system of six on-chip LDO regulators within a commercial high performance portable device. The proposed system is the first successful silicon demonstration of stable fully integrated parallel analog LDO regulators.


Distributed power delivery Voltage regulators On-chip LDO PVT variations Adaptive compensation Adaptive biasing Stability 28 nm 



This research is supported in part by the Binational Science Foundation under Grant No. 2012139, the National Science Foundation under Grant No. CCF-1329374, and by a grant from Qualcomm Corporation.


  1. 1.
    Kose, S., Tam, S., Pinzon, S., McDermott, B., & Friedman, E. G. (2013). Active filter based hybrid on-chip DC–DC converters for point-of-load voltage regulation. IEEE Transactions on Very Large Scale Integration (VLSI) Circuits, 21(4), 680–691.CrossRefGoogle Scholar
  2. 2.
    Kose, S., & Friedman, E. G. (2012). Distributed on-chip power delivery. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2(4), 704–713.CrossRefGoogle Scholar
  3. 3.
    Degrauwe, M. G., Rijmenants, J., Vittoz, E. A., & de Man, H. J. (1982). Adaptive biasing CMOS amplifiers. IEEE Journal of Solid-State Circuits, 17(3), 522–528.CrossRefGoogle Scholar
  4. 4.
    Huang, W.-J., & Liu, S.-I. (2008). Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array. IET Electronics Letters, 2(3), 306–316.Google Scholar
  5. 5.
    Leung, K. N., & Mok, P. K. T. (2003). A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation. IEEE Journal of Solid-State Circuits, 38(10), 1691–1702.CrossRefGoogle Scholar
  6. 6.
    Chava, C. K., & Silva-Martinez, J. (2004). A frequency compensation scheme for LDO voltage regulators. IEEE Transactions on Circuits and Systems I: Regular Papers, 51(6), 1041–1050.CrossRefGoogle Scholar
  7. 7.
    Fan, X., Mishra, C., & S.-Sinencio, E. (2005). Single Miller capacitor frequency compensation technique for low-power multistage amplifiers. IEEE Journal of Solid-State Circuits, 40(3), 584–592.CrossRefGoogle Scholar
  8. 8.
    Hazucha, P., et al. (2005). Area-efficient linear regulator with ultra-fast load regulation. IEEE Journal of Solid-State Circuits, 40(4), 933–940.CrossRefGoogle Scholar
  9. 9.
    Milliken, R. J., S.-Martinez, J., & S.-Sinencio, E. (2007). Full On-Chip CMOS low-dropout voltage regulator. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(9), 1879–1890.CrossRefGoogle Scholar
  10. 10.
    Man, T. Y., Mok, P. K. T., & Chan, M. (2007). A high slew-rate push–pull output amplifier for low-quiescent current low-dropout regulators with transient–response improvement. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(9), 755–759.CrossRefGoogle Scholar
  11. 11.
    Al-Shyoukh, M., Lee, H., & Perez, R. (2007). A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation. IEEE Journal of Solid-State Circuits, 42(8), 1732–1742.CrossRefGoogle Scholar
  12. 12.
    Leung, K. N., Ng, Y. S., Yim, K. Y., & Or, P. Y. (2007). An adaptive current-boosting voltage buffer for low-power low dropout regulators. Proceeding of the IEEE Conference on Electron Devices and Solid-State Circuits, pp. 485–488.Google Scholar
  13. 13.
    Lam, Y.-H., & Ki, W.-H. (2008). A 0.9 V 0.35 μm adaptively biased CMOS LDO regulator with fast transient response. Proceedings of the IEEE International Solid-State Circuits Conference, pp. 442–626.Google Scholar
  14. 14.
    El-Nozahi, M., Amer, A., Torres, J., Entesari, K., & Sanchez Sinencio, E. (2010). High PSR low Drop-Out regulator with feedforward ripple cancellation technique. IEEE Journal of Solid-State Circuits, 45(3), 565–577.CrossRefGoogle Scholar
  15. 15.
    Guo, J., & Leung, K. N. (2010). A 6-μW Chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology. IEEE Journal of Solid-State Circuits, 45(9), 1896–1905.CrossRefGoogle Scholar
  16. 16.
    Ho, M., Leung, K. N., & Mac, K.-L. (2010). A low-power fast-transient 90-nm low-dropout regulator with multiple small-gain stages. IEEE Journal of Solid-State Circuits, 45(11), 2466–2475.Google Scholar
  17. 17.
    Or, P. Y., & Leung, K. N. (2010). An output-capacitorless low-dropout regulator with direct voltage-spike detection. IEEE Journal of Solid-State Circuits, 45(2), 458–466.CrossRefGoogle Scholar
  18. 18.
    Rincon-Mora, G. A., & Allen, P. E. (1998). A low-voltage, low quiescent current, low drop-out regulator. IEEE Journal of Solid-State Circuits, 33(1), 36–44.CrossRefGoogle Scholar
  19. 19.
    Hattori, T., & et al. (2006). A power management scheme controlling 20 power domains for a single-chip mobile processor. Proceedings of the IEEE International Solid-State Circuits Conference, pp. 542–543.Google Scholar
  20. 20.
    Vaisband, I., & Friedman, E. G. (2013). heterogeneous methodology for energy efficient distribution of on-chip power supplies. IEEE Transactions on Power Electronics, 28(9), 4267–4280.CrossRefGoogle Scholar
  21. 21.
    Lee, Y.-H., Peng, S.-Y., Chiu, C.-C., Wu, A. C.-H., Chen, K.-H., Lin, Y.-H., et al. (2013). A low quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40 nm soc for MIPS performance improvement. IEEE Journal of Solid-State Circuits, 48(4), 1018–1030.CrossRefGoogle Scholar
  22. 22.
    Li, P. (2012). Design and analysis of IC power delivery. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 664–666.Google Scholar
  23. 23.
    Lai, S., Yan, B., & Li, P. (2012). Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 247–254.Google Scholar
  24. 24.
    Lai, S., & Li, P. (2012). A fully on-chip area-efficient CMOS low-dropout regulator with load regulation. Analog Integrated Circuits and Signal Processing, 72(2), 925–1030.CrossRefMathSciNetGoogle Scholar
  25. 25.
    Lai, S., Yan, B., & Li, P. (2013).Localized stability checking and design of IC power delivery with distributed voltage regulators. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(9), 1321–1334.CrossRefGoogle Scholar
  26. 26.
    D’Souza, A. J., Singh, R., Prabhu, J. R., Chowdary, G., Seedher, A., Somayajula, S., Nalam, N. R., Cimaz, L., Le Coq, S., Kallam, P., Sundar, S., Cheng, S., Tumati, S., & Huang, W. (2011). A fully integrated power-management solution for a 65 nm CMOS cellular handset chip. Proceedings of the IEEE International Solid-State Circuits Conference, pp. 382–384.Google Scholar
  27. 27.
    Bulzacchelli, J. F., Toprak-Deniz, Z., Rasmus, T. M., Iadanza, J. A., Bucossi, W. L., Kim, S., et al. (2012). Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout voltage. IEEE Journal of Solid-State Circuits, 47(4), 863–874.CrossRefGoogle Scholar
  28. 28.
    Lima, F., Geraldes, A., Marques, T., Ramalho, J. N., & Casimiro, P. (2003). Embedded CMOS distributed voltage regulator for large core lads. Proceedings of the IEEE European Solid-State Circuits Conference, pp. 521–524.Google Scholar
  29. 29.
    Nassif, S. R. (2008). Power grid analysis benchmarks. Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 376–381.Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringUniversity of RochesterRochesterUSA
  2. 2.Department of Electrical EngineeringUniversity of South FloridaTampaUSA
  3. 3.Qualcomm CorporationRaleighUSA

Personalised recommendations