Abstract
An edge-combining delay-locked loop (ECDLL) frequency multiplier with multi phase outputs is presented. In contrast to architectures based on phase-locked loop, the proposed frequency multiplier produces outputs with 25 % duty cycle without operating at multiple times of the required output frequency. Level of reference spurs at the DLL outputs is reduced by a static phase error suppression technique. In this technique, reset pulse of phase detector (PD) is used to steer charge pump (CP) currents to a dummy branch during idle interval of PD and eliminate CP current mismatch effect. This paper also presents a delay cell with linear transfer curve to increase control range of delay line and provide rather constant loop parameters in a rail-to -rail tuning voltage range. Employing the mentioned techniques, an ECDLL with a frequency multiplication factor of N = 14 and 4-phase outputs has been designed in a 0.18 μm CMOS technology. Post-layout simulation results of the designed ECDLL have been provided in this technology. At 1.4 GHz output frequency, static phase offset simulation result shows a reference spur level reduction of about 18 dB compared to conventional PD/CP circuit. From Monte Carlo simulations, which consider effect of delay mismatch among the delay cells, mean spur level is about −40 dBc. Phase noise analysis, based on a discrete-time (Z-domain) model, for the multiphase ECDLL has been provided and its predictions are close to the simulation results. Phase noise at 10, 100 kHz and 1 MHz frequency offsets is −102.7, −112.5 and −120.1 dBc/Hz, respectively. The circuit consumes 20 mW from a 1.8 V supply.
Similar content being viewed by others
References
Chien, G., & Gray, P. R. (2000). A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications. IEEE Journal of Solid-State Circuits, 35(12), 1996–1999.
Hossain, M., Aquil, F., Chau, P. S., et al. (2014). A fast-lock, jitter filtering all-digital DLL based burst-mode memory interface. IEEE Journal of Solid-State Circuits, 49(4), 1048–1062.
Ok, S., Chung, K., Koo, J., Kim, S. W., & Kim, C. (2010). An anti-harmonic programmable DLL-based frequency multiplier for dynamic frequency scaling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(7), 1130–1134.
Cheng, K. H., & Lo, Y.-L. (2007). A fast-lock wide-range delay-locked loop using frequency-range selector for multiphase clock generator. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(7), 561–565.
Chen, Y. G., Tsao, H. W., & Hwang, C. S. (2013). A fast-locking all-digital Deskew buffer with duty-cycle correction. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(2), 270–280.
Lip-Kai, S., Sulaiman, M. S., & Yusoff, Z. (2008). A fast-lock delay-locked loop architecture with improved precharged PFD. Analog Integrated Circuits and Signal Processing, 55, 149–154.
Kj, Hsiao, & Lee, T. C. (2009). An 8-GHz to 10-GHz distributed DLL for multiphase clock generation. IEEE Journal of Solid-State Circuits, 44(9), 2478–2487.
Park, H. G., Kim, S., & Lee, K. Y. (2013). A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock. Analog Integrated Circuits and Signal Processing, 74, 355–364.
Lee, H. W., & Kim, C. (2014). Survey and analysis of delay-locked loops used in dram interfaces. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(4), 701–711.
Lin, W., Teng, K., and Liu, S. (2009). A delay-locked loop with digital background calibration. IEEE Asian Solid-State Circuits Conference (A-SSCC), 317–320.
Casha, O., Grech, I., Badets, F., et al. (2009). Analysis of the spur characteristics of edge-combining DLL-based frequency multipliers. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(2), 132–136.
Hwang, S., Kim, K. M., Kim, J., et al. (2013). A self-calibrated DLL-based clock generator for an energy-aware EISC processor. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(3), 575–579.
Chang, H., Chang, J., Kuo, C. Y., & Liu, S. I. (2006). A 0.7-2-GHz self-calibrated multiphase delay-locked loop. IEEE Journal of Solid-State Circuits, 41(5), 1051–1061.
Liao, F. R., & Lu, S. (2010). A programmable edge-combining DLL with a current-splitting charge pump for spur suppression. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(12), 946–950.
Chuang, C. N., & Liu, S. I. (2008). A 3–8 GHz delay-locked loop with cycle jitter calibration. IEEE Transactions on Circuits and Systems II: Express Briefs, 55(11), 1094–1098.
Chuang, C. N., & Liu, S. I. (2007). A 0.5–5-GHz wide-range multiphase DLL with a calibrated charge pump. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(11), 939–943.
Cf, Liang, Chen, S. H., & Liu, S. I. (2008). A digital calibration technique for charge pumps in phase-locked systems. IEEE Journal of Solid-State Circuits, 43(2), 390–398.
Ojani, A., Mesgarzadeh, B., Alvandpour, A. (2012). A DLL-based injection-locked frequency synthesizer for WiMedia UWB. IEEE International Symposium Circuits and Systems (ISCAS), 2027–2030.
Chang, R. H., Chen, H. M., & Huang, P. J. (2008). A multiphase-output delay-locked loop with a novel start-controlled phase/frequency detector. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(9), 2483–2490.
Chuang, C. N., & Liu, S. I. (2009). A 20-MHz to 3-GHz wide-range multiphase delay-locked loop. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(11), 850–854.
Mirzaei, A., Darabi, H., Leete, J. C., & Chang, Y. (2010). Analysis and optimization of direct-conversion receivers with 25 % duty-cycle current-driven passive mixers. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(9), 2353–2366.
Ghaffari, A., Klumperink, E. A., Soer, M. C., & Nauta, B. (2011). Tunable high-Q N-path band-pass filters: Modeling and verification. IEEE Journal of Solid-State Circuits, 46(5), 998–1010.
Darabi, H., Mirzaei, A., & Mikhemar, M. (2011). Highly integrated and tunable RF front ends for reconfigurable multiband transceivers: A tutorial. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(9), 2038–2050.
Mirzaei, A., Darabi, H., & Murphy, D. (2012). Architectural evolution of integrated M-phase high-Q bandpass filters. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(1), 52–65.
Mirzaei, A., Darabi, H., Yazdi, A., et al. (2011). A 65 nm CMOS quad-band SAW-less receiver SoC for GSM/GPRS/EDGE. IEEE Journal of Solid-State Circuits, 46(4), 950–964.
Chang, H., Lin, J. W., Yang, C. Y., & Liu, S. I. (2002). A wide-range delay-locked loop with a fixed latency of one clock cycle. IEEE Journal of Solid-State Circuits, 37(8), 1021–1027.
Chen, C. C., Chang, J. Y., & Liu, S. I. (2007). A DLL-based variable-phase clock buffer. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(12), 1072–1076.
De Muer, B., & Steyaert, M. S. (2002). A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800. IEEE Journal of Solid-State Circuits, 37(7), 835–844.
Saeedi, S., & Atarodi, M. (2010). Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation. Analog Integrated Circuits and Signal Processing, 64, 103–113.
Rategh, H. R., Samavati, H., & Lee, T. H. (2000). A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver. IEEE Journal of Solid-State Circuits, 35(5), 780–787.
Ye, S., & Galton, I. (2004). Techniques for phase noise suppression in recirculating DLLs. IEEE Journal of Solid-State Circuits, 39(8), 1222–1230.
Liao, R. R., & Lu, S. S. (2012). A waveform-dependent phase-noise analysis for edge-combining DLL frequency multipliers. IEEE Transactions on Microwave Theory and Techniques, 60(4), 1086–1096.
Hastings, A. (2001). The art of analog layout. Upper Saddle River: Prentice Hall.
Ryu, K. H., Jung, D. H., & Jung, S. O. (2010). A DLL based clock generator for low-power mobile SoCs. IEEE Transactions on Consumer Electronics, 56(3), 1950–1956.
Lee, T. C., & Hsiao, K. J. (2006). The design and analysis of a DLL-based frequency synthesizer for UWB application. IEEE Journal of Solid-State Circuits, 41(6), 1245–1252.
Kuo, C. H., Lai, H. J., & Lin, M. F. (2011). A multi-band fast-locking delay-locked loop with jitter-bounded feature. IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, 58(1), 51–59.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Hassani, M., Saeedi, S. Edge-combining multi-phase DLL frequency multiplier with reduced static phase offset and linearized delay transfer curve. Analog Integr Circ Sig Process 82, 705–718 (2015). https://doi.org/10.1007/s10470-015-0495-1
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-015-0495-1