Accurate delay models of CMOS CML circuits for design optimization
This paper presents accurate delay models of current-mode logic (CML) circuits for equation-based circuit optimization. We propose accurate edge-rate-dependent delay models of a CML buffer, a latch, and a multiplexer. Newly proposed delay models have compatibility with geometric programming and scalability for the hierarchical design of CML-based circuits, thereby enabling true constraint-driven equation-based design optimization. In order to validate these models, we show the modeling errors of unit CML gates over a wide range of delay and edge rates. N-stage CML buffers and a 28 Gb/s serializer in 45 nm CMOS technology are optimized for minimum power dissipation. The numerical experiments indicates that the proposed delay models can guarantee the intended operation of CML-based circuits when used in the equation-based design optimization.
KeywordsCMOS Current-mode logic gates Delay model Geometric programming Serializer
- 2.Colleran, D., Portmann, C., Hassibi, A., Crusius, C., Mohan, S., Boyd, S., et al. (2003). Optimization of phase-locked loop circuits via geometric programming. Proc. IEEE Custom Integrated Circuits Conference, 377–380.Google Scholar
- 8.Boyd, S., & Vendenberghe, L. (2003). Convex optimization. Cambridge: Cambridge University Press.Google Scholar
- 11.Sturm, J., F. (1999). Using SeDuMi 1.02, a MATLAB toolbox for optimization over symmetric cones. Optimization Methods and Software, 11–12, 625–633.Google Scholar
- 12.Gray, P., Hurst, P., Lewis, S., & Meyer, R. (2010). Analysis and design of analog integrated circuits. New York: Wiley.Google Scholar