Skip to main content
SpringerLink
Log in

Background calibration of integrator leakage in discrete-time delta-sigma modulators

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents an integration-leakage calibration technique for the switched-capacitor integrators in a delta-sigma modulator (DSM). Integrators realized with low-gain opamps are lossy. A DSM that uses lossy integrators exhibits a degraded signal-to-quantization-noise ratio. To calibrate an integrator, its integration leakage is detected in the digital domain, and the leakage compensation is applied to the same integrator in the analog domain. The proposed scheme can calibrate all integrators in a discrete-time DSM of any form. It can be proceed in the background without interrupting the normal DSM operation. The design considerations for the proposed calibration scheme are discussed. Design cases of a 1st-order, a 2nd-order, and a 3rd-order DSM are demonstrated and simulated.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24
Fig. 25

Similar content being viewed by others

References

  1. Young, I. A. (2010). Analog mixed-signal circuits in advanced nano-scale CMOS technology for microprocessors and SoCs. In: European Solid-State Circuits Conference (ESSCIRC), pp. 61–70.

  2. Yoshizawa, H., Yabe, T., & Temes, G. C. (2011). High-precision switched-capacitor integrator using low-gain opamp. Electronics Letters, 47(5), 315.

    Article  Google Scholar 

  3. Musah, T., & Moon, U. K. (2011). Correlated level shifting integrator with reduced sensitivity to amplifier gain. Electronics Letters, 47(2), 91.

    Article  Google Scholar 

  4. Peng, X., Sansen, W., Hou, L., Wang, J., & Wu, W. (2011). Impedance adapting compensation for low-power multistage amplifiers. IEEE Journal of Solid-State Circuits, 46(2), 445–451.

    Article  Google Scholar 

  5. Huang, H. & Lee, E. K. F. (2001). A 1.2 V direct background digital tuned continuous-time bandpass sigma-delta modulator. In: European Solid-State Circuits Conference (ESSCIRC), pp. 526–529.

  6. Lu, C. Y., Silva-Rivas, J. F., Kode, P., Silva-Martinez, J., & Hoyos, S. (2010). A sixth-order 200 MHz IF bandpass sigma-delta modulator with over 68 dB SNDR in 10 MHz bandwidth. IEEE Journal of Solid-State Circuits, 45(6), 1122–1136.

    Article  Google Scholar 

  7. Shu, Y. S., Song, B. S., Bacrania K. (2008). A 65 nm CMOS CT \(\Delta \Sigma\) modulator with 81 dB DR and 8 MHz BW auto-tuned by pulse injection. In: IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 500–631.

  8. Duggal, A. R., Sonkusale, S., & Lachapelle, J. (2011). Calibration of delta-sigma data converters in synchronous demodulation sensing applications. IEEE Sensors Journal, 11(1), 16–22.

    Article  Google Scholar 

  9. Lee, S. C., & Chiu, Y. (2014). A 15-Mhz bandwidth 1–0 MASH \(\Sigma \Delta\) ADC with nonlinear memory error calibration achieving 85-dBc SFDR. IEEE Journal of Solid-State Circuits, 49(3), 695–707.

    Article  Google Scholar 

  10. Schreier, R. (1994). On the use of chaos to reduce idle-channel tones in delta-sigma modulators. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 41(8), 539–547.

    Article  Google Scholar 

  11. Zhang, Y., Chen, C. H., & Temes, G. C. (2013). Accuracy-enhanced switched-capacitor stages using low-gain opamps. Electronics Letters, 49(1), 22–23.

    Article  Google Scholar 

  12. Huang, C. C., & Wu, J. T. (2005). A background comparator calibration technique for flash analog-to-digital converters. IEEE Transactions on Circuits and Systems I: Regular Papers, 52(9), 1732–1740.

    Article  Google Scholar 

  13. Figueiredo, M., Santos-Tavares, R., Santin, E., Ferreira, J., Evans, G., & Goes, J. (2011). A two-stage fully differential inverter-based self-biased CMOS amplifier with high efficiency. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(7), 1591–1603.

    Article  MathSciNet  Google Scholar 

  14. Wu, S. H., & Wu, J. T. (2013). A 81-dB dynamic range 16-Mhz bandwidth \(\Delta \Sigma\) modulator using background calibration. IEEE Journal of Solid-State Circuits, 48(9), 2170–2179.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan

    Su-Hao Wu & Jieh-Tsorng Wu

Authors
  1. Su-Hao Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jieh-Tsorng Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Su-Hao Wu.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Wu, SH., Wu, JT. Background calibration of integrator leakage in discrete-time delta-sigma modulators. Analog Integr Circ Sig Process 81, 645–655 (2014). https://doi.org/10.1007/s10470-014-0421-y

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-014-0421-y

Keywords

Search

Navigation