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A 12-bit 100 MS/s pipelined SAR ADC with addition-only digital error correction

  • Mixed Signal Letter
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Abstract

A new redundant successive approximation register (SAR) ADC architecture with digital error correction is presented to avoid the comparator offset issue and subtraction operations. A 2-channel 12-bit 100 MS/s SAR ADCs based on the proposed architecture with voltage-controlled delay lines based time-domain comparator is designed in a 65 nm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.81 dB (11.47 ENOB), a spurious free dynamic range (SFDR) of 80.33 dB for a near Nyquist input at 100 MS/s, while dissipating 11 mW from a 1.2-V supply, giving a FOM of 38.8 fJ/Conversion-step.

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  1. School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu, China

    Hua Fan

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  1. Hua Fan
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Correspondence to Hua Fan.

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Fan, H. A 12-bit 100 MS/s pipelined SAR ADC with addition-only digital error correction. Analog Integr Circ Sig Process 81, 325–339 (2014). https://doi.org/10.1007/s10470-014-0389-7

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  • DOI: https://doi.org/10.1007/s10470-014-0389-7

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