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Low-power 10 Gb/s inductorless inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS


This study presents an inductorless 10 Gb/s transimpedance amplifier (TIA) implemented in a 40 nm CMOS technology. The TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows measured optical sensitivities of −17.7 and −16.2 dBm at BER = 10−12 for data rates of 8 and 10 Gb/s, respectively. The TIA has a simulated transimpedance gain of 47 dBΩ, 8 GHz bandwidth with 0.45 pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002 mm2 whereas the complete optical receiver occupies a chip area of 0.16 mm2. The power consumption of the TIA is only 2.03 mW and the complete chip dissipates 17 mW for a 1.1 V single supply voltage. The complete optical receiver has a measured transimpedance gain of 57.5 dBΩ.

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Correspondence to Mohamed Atef.

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Atef, M., Zimmermann, H. Low-power 10 Gb/s inductorless inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS. Analog Integr Circ Sig Process 76, 367–376 (2013).

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  • Optical receiver
  • Transimpedance amplifier
  • Optoelectronics