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Gate-leakage compensation scheme for programmable SI-DAC of ΣΔ modulator in deep sub-micron

  • Mixed Signal Letter
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Abstract

A gate-leakage compensation scheme is proposed to solve the gate-leakage current issue caused by large-size current-source transistors in multi-bit switched-current (SI) DACs of the continuous-time ΣΔ modulator in deep sub-micron process without extra power consumption. To cover wide current range due to variable coefficients in different modes, the programmable SI-DAC architecture with 2-bit digital controlled unit cells is proposed. Implemented in 65 nm CMOS, the simulated results verify that the proposed scheme solves the gate-leakage issue and the modulator achieves tremendously high performance of 84.5 dB SQNDR and 94.6 dB SFDR with almost 14 and 19 dB improvement in SQNDR and SFDR, respectively.

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Acknowledgments

This work was supported in part by the National Science and Technology Major Projects of China (Grant 2012ZX03004007) and in part by the National Natural Science Foundation of China (Grant 61020106006).

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Authors and Affiliations

  1. Institute of Microelectronics, Tsinghua University, Beijing, China

    Yang Xu, Baoyong Chi & Zhihua Wang

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  1. Yang Xu
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  2. Baoyong Chi
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  3. Zhihua Wang
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Correspondence to Yang Xu.

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Xu, Y., Chi, B. & Wang, Z. Gate-leakage compensation scheme for programmable SI-DAC of ΣΔ modulator in deep sub-micron. Analog Integr Circ Sig Process 76, 155–160 (2013). https://doi.org/10.1007/s10470-013-0073-3

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  • DOI: https://doi.org/10.1007/s10470-013-0073-3

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