Abstract
A base-4 architecture for folding and interpolating ADC is proposed. It employs cascaded folding and interpolating topology with both the folding factors and interpolating factors of 4. Duo to that the base-4 folding and interpolating has an intrinsic relationship with the quantization process which is base-2, the architecture requires only 2 × N + 6 comparators for an N-bit ADC. What’s more, the coarse flash ADC can be eliminated because all the most significant bits can be conveniently extracted from the intermediate signals as the “byproduct” of the folding amplifiers. In addition, the base-4 architecture can be extended to higher resolution easily because of the modularized and unified configuration. This architecture is implemented with a 1 GS/s 8-bit ADC in 0.35 μm SiGe BiCMOS process. Measurement results reveal the chip exhibits DNL of 0.30/−0.26 LSB and INL of 0.80/−0.80 LSB. The ENOB is 6.9 LSB at 10.1 MHz input. The SNDR is above 42 dB over the first and the second Nyquist zone. The SFDR is above 45 dB over the first Nyquist zone and the second Nyquist zone. The ERBW is over 1.2 GHz.
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References
Yu, H., & Chang, M. C. F. (2008). A 1-V 1.25-GS/s 8-bit self-calibrated flash ADC in 90-nm digital CMOS. IEEE Transaction on Circuits System II, Express Briefs, 55(7), 668–672.
Pan, H., & Abidi, A. A. (2004). Signal folding in A/D converters. IEEE Transaction on Circuits System I, Regular Papers, 51(1), 3–14.
Taft, R. C., Menkus, C. A., Tursi, M. R., & Hidri, O. (2004). A 1.8 V 1.6 GS/s 8b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency. IEEE Journal of Solid-State Circuits, 39(12), 2107–2115.
Choe, M. J., Song, B. S., & Bacrania, K. (2001). A 8-b 100-MSample/s CMOS pipeline folding ADC. IEEE Journal of Solid-State Circuit, 36(3), 184–194.
Taft, R. C., Francese, P. A., Tursi, M. R., Hidri, O., et al. (2009). A 1.8 V 1.0 GS/s 10b self-calibrating unified folding–interpolating ADC with 9.1 ENOB at Nyquist frequency. IEEE Journal of Solid-State Circuits, 44(12), 3294–3304.
Vorenkamp, P., & Roovers, R. (1997). A 12-b 60-MSample cascaded folding and interpolating ADC. IEEE Journal of Solid-State Circuits, 32(12), 1876–1886.
Vessal, F., & Salama, C. A. T. (2004). An 8-bit 2-Gsamples/s folding–interpolating analog-to-digital converter in SiGe technology. IEEE Journal of Solid-State Circuits, 39(1), 238–241.
Flynn, M. P., & Sheahan, B. (1998). A 400-MSample/s, 6-b CMOS folding and interpolating ADC. IEEE Journal of Solid-State Circuit, 33(12), 1932–1938.
Ghetmiri, S., & Salama, C. A. T. (2010). An 8-bit 12.5-GSample/s SiGe ADC. Analog Integrated Circuits and Signal Processing, 63, 381–395.
Razzaghi, A., Tam, S. W., Kalkhoran, P., et al. (2008). A single-channel 10b 1GS/s ADC with 2-cycle latency using pipelined cascaded folding architecture. In Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), pp. 265–268.
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Jiang, F., Wu, D., Zhou, L. et al. An 8-bit 1 GS/s folding and interpolating ADC with a base-4 architecture. Analog Integr Circ Sig Process 76, 139–146 (2013). https://doi.org/10.1007/s10470-013-0072-4
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DOI: https://doi.org/10.1007/s10470-013-0072-4