Abstract
An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs.
This is a preview of subscription content, log in via an institution to check access.
References
Liu, C.-C., Chang, S.-J., Huang, G.-Y., & Lin, Y.-Z. (2010). A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE Journal of Solid-State Circuits, 45(4), 731–740.
Zhu, Y., Chan, C.-H., Chio, U.-F., Sin, S.-W., Seng-Pan, U., Martins, R. P., et al. (2010). A 10-bit 100-MS/s reference-free SAR ADC n 90 nm CMOS. IEEE Journal of Solid-State Circuits, 45(6), 1111–1121.
Wei, H., Chan, C., & Chio, U. (2011). A 0.024 mm2 8 b 400 MS/s SAR ADC with 2b/cycle and resistive DAC in 65 nm CMOS. In IEEE International Solid-State Circuits Conference, pp. 188–189.
Ginsburg, B. P., & Chandrakasan, A. P. (2007). 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC. IEEE Journal of Solid-State Circuits, 42(4), 739–747.
Liu, W., Chang, Y., Hsien, S. K., Chen, B. W., Lee, Y. P., Chen, W. T., Yang, T. Y., Ma, G. K., & Chiu, Y. (2009). A 600 MS/s 30 mW 0.13 μm CMOS ADC array achieving over 60 dB SFDR with adaptive digital equalization. In IEEE International Solid-State Circuits Conference, pp. 82–83.
Liu, C.-C., Chang, S.-J., Huang, G.-Y., Lin, Y.-Z., Huang, C.-M., Huang, C.-H., Bu, L., & Tsai, C.-C. (2010). A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation. In IEEE International Solid-State Circuits Conference, pp. 386–389.
Jiang, S., Do, M. A., Yeo, K. S., & Lim, W. M. (2008). An 8-bit 200-M sample/s pipelined ADC with mixed-mode front-end S/H circuit. IEEE Transactions on Circuits and Systems I, 55(6), 1430–1440.
Goll, B., & Zimmermann, H. (2009). A 65 nm CMOS comparator with modified latch to achieve 7 GHz/1.3 mW at 1.2 V and 700 MHz/47 μW at 0.6 V. In IEEE International Solid-State Circuits Conference, pp. 327–329.
Jiang, T., Liu, W., Zhong, F. Y., Zhong, C., Kangmin, H., & Chiang, P. Y. (2012). A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS. IEEE Journal of Solid-State Circuits, 47(10), 2444–2453.
Yang, J., Naing, T. L., & Brodersen, R. W. (2010). A 1 GS/s 6 bit 6.7 mW successive approximation ADC using asynchronous processing. IEEE Journal of Solid-State Circuits, 45(8), 1469–1478.
Mesgaranim, A. (2011). A single channel 6-Bit 900 MS/s 2-Bits per stage asynchronous binary search ADC. In IEEE 54th International Midwest Symposium on Circuits and Systems, pp. 1–4.
Acknowledgments
This work was supported by the National Natural Science Foundation of China (61234002, 61006028), the National High-tech Program of China (2012AA012302, 2013AA014103) and Ph.D. Programs Foundation of Ministry of Education of China (20120203110017).
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Zhu, Z., Wang, Q., Xiao, Y. et al. An 8-bit 208 MS/s SAR ADC in 65 nm CMOS. Analog Integr Circ Sig Process 76, 129–137 (2013). https://doi.org/10.1007/s10470-013-0071-5
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-013-0071-5