Analog Integrated Circuits and Signal Processing

, Volume 74, Issue 2, pp 453–460 | Cite as

Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes

Article

Abstract

A CMOS distributed amplifier (DA) with low-power and flat and high power gain (S21) is presented. In order to decrease noise figure (NF) an RL terminating network used for the gate transmission line instead of single resistance. Besides, a flat and high S21 is achieved by using the proposed cascade gain cell consist of a cascode-stage with bandwidth extension capacitor. In the high-gain mode, under operation condition of Vdd = 1.2 V and the overall current consumption of 7.8 mA, simulation result shown that the DA consumed 9.4 mW and achieved a flat and high S21 of 20.5 ± 0.5 dB with an average NF of 6.5 dB over the 11 GHz band of interest, one of the best reported flat gain performances for a CMOS UWB DA. In the low-gain mode, the DA achieved average S21 of 15.5 ± 0.25 dB and an average NF of 6.6 dB with low power consumption (PDC) of 3.6 mW, the lowest PDC ever reported for a CMOS DA or LNA with an average gain better than 10 dB.

Keywords

CMOS Distributed amplifier Cascade High gain Low power 

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Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  1. 1.Electrical Engineering DepartmentKerman Graduate University of TechnologyKermanIran
  2. 2.Electrical Engineering DepartmentShahid Bahonar University of KermanKermanIran

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