Analog Integrated Circuits and Signal Processing

, Volume 74, Issue 2, pp 355–364 | Cite as

A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock

Article

Abstract

This paper presents a wide frequency range CDR circuit for second generation AiPi+ intra-panel interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with conventional AiPi+. The DLL-based CDR architecture is adopted to generate multi-phase clocks. We propose a simple scheme for a frequency detector (FD) to overcome the limited frequency range and false lock problem of a conventional delay-locked loop (DLL) to reduce the complexity. In addition, a duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatches between rising and falling time of delay cells in the VCDL. Also, the proposed simple DLL architecture comprised of frequency and phase detectors has better process-portability. The proposed CDR is implemented in 0.18 μm technology and the active die area is 660 × 250 μm. The implemented DLL covers a frequency range from 62 to 128 MHz, which is limited only by the characteristics of the delay cell. The peak-to-peak jitter is less than 13 ps when the input frequency is 128 MHz, and the power consumption of the CDR except the input buffer, equalizer, and de-serializer is 5.94 mW from the supply voltage of 1.8 V.

Keywords

Delay-locked loop Wide frequency range Clock and data recovery Multi-phase Frequency detection False locking problem Jitter 

References

  1. 1.
    Nam, H., Oh, K. Y., Kim, S. K., Kim, N. D., & Kim, S. S. (2009). A cost-effective 60 Hz FHD LCD using 800 Mbps AiPi technology. KIDS Journal of Information Display, 10(1), 37–44.CrossRefGoogle Scholar
  2. 2.
    Yamguchi, K., Hori, Y., Nakajima, K., Suzuki, K., Mizuno, M., Hayama, H. (2009). A 2.0 Gb/s clock-embedded interface for full-HD 10b 120 Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. IEEE ISSCC Digest of Technical Papers, pp. 192–193.Google Scholar
  3. 3.
    Lee, T. H., Donnelly, K. S., Ho, J. T. C., Zerbe, J., Johnson, M. G., & Ishikawa, T. (1994). A 2.5 V CMOS delay-locked loop for an 18 Mbit, 500 MB/s DRAM. IEEE Journal of Solid-State Circuits, 29, 1491–1496.CrossRefGoogle Scholar
  4. 4.
    Sidiropoulos, S., & Horowiz, M. A. (1997). A semi-digital dual delay-locked loop. IEEE Journal of Solid-State Circuits, 32, 1683–1692.CrossRefGoogle Scholar
  5. 5.
    Coban, A. L., Koroglu, M. H., & Ahmed, K. A. (2005). A 2.5–3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs. IEEE Journal of Solid-State Circuits, 40(9), 1940–1947.CrossRefGoogle Scholar
  6. 6.
    Jung, Y. J., Lee, S. W., Shim, D., Kim, W., & Cho, S. I. (2001). A dual-loop delay-locked loop using multiple voltage-controlled delay lines. IEEE Journal of Solid-State Circuits, 36(5), 784–791.CrossRefGoogle Scholar
  7. 7.
    Moon, Y., Choi, J., Lee, K., Jeong, D. K., & Kim, M. K. (2000). An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. IEEE Journal of Solid-State Circuits, 35(3), 377–384.CrossRefGoogle Scholar
  8. 8.
    Chung, C. C., & Lee, C. Y. (2004). A new DLL-based approach for all-digital multiphase clock generation. IEEE Journal of Solid-State Circuits, 39(3), 469–475.CrossRefGoogle Scholar
  9. 9.
    Chang, H. H., Lin, J. W., Yang, C. Y., & Liu, S. I. (2002). A wide-range delay locked loop with a fixed latency of one clock cycle. IEEE Journal of Solid-State Circuits, 37(8), 1021–1027.CrossRefGoogle Scholar
  10. 10.
    Minami, K., et al. (2000). A 1 GHz portable digital delay-locked loop with infinite phase capture ranges. IEEE ISSCC Digest of Technical Papers, pp. 350–351.Google Scholar
  11. 11.
    Foley, D. J., & Flynn, M. P. (2001). CMOS DLL-based clock synthesizer and temperature-compensated tunable oscillator. IEEE Journal of Solid-State Circuits, 36(3), 417–423.CrossRefGoogle Scholar
  12. 12.
    Gierkink, S. L. J. (2008). Low-spur, low-phase-noise clock multiplier based on a combination of PLL and recirculating DLL with dual-pulse ring oscillator and self-correcting charge pump. IEEE Journal of Solid-State Circuits, 43(12), 2967–2976.CrossRefGoogle Scholar
  13. 13.
    Huh, H., Koo, Y., Lee, K.-Y., Ok, Y., Lee, S., Kwon, D., et al. (2005). Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer. IEEE Journal of Solid-State Circuits, 40(11), 2228–2236.CrossRefGoogle Scholar
  14. 14.
    Song, E., Lee, S.-W., Lee, J.-W., Park, J., & Chae, S.-I. (2004). A reset-free anti-harmonic delay-locked loop using a cycle period detector. IEEE Journal of Solid-State Circuits, 39(11), 2055–2061.CrossRefGoogle Scholar
  15. 15.
    Rhee, R.W., Ainspan, H., Rylov, S., Rylyakov, A., Beakes, M., Friedman, D., Gowda, S., Soyuer, M. (2003). A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003, pp. 81–84.Google Scholar
  16. 16.
    Cheng, K.-H., & Lo, Y.-L. (2007). A fast-lock wide-range delay-locked loop using frequency-range selector for multiphase clock generator. IEEE Transactions on Circuits and Systems. Part II, 54(7), 561–565.CrossRefGoogle Scholar
  17. 17.
    Young, A., Greason, J.K., & Wong, K.L. (1992). A PLL clock generator with 5 to 110 MHz of lock range for microprocessors. IEEE Journal of Solid-State Circuits, SC-27: 1599–1607.Google Scholar
  18. 18.
    Chen, C.-C., & Liu, S.-I. (2008). An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line. IEEE Journal of Solid-State Circuits, 43(11), 2413–2421.CrossRefGoogle Scholar
  19. 19.
    Chang, R.C.-H., Chen, H.-M., & Huang, P.-J. (2008) A multiphase-output delay-locked loop with a novel start-controlled phase/frequency detector. IEEE Transactions on Circuits and Systems–I, 55(9): 2483–2490.Google Scholar
  20. 20.
    Lu, C.-T., Hsieh, H.-H., & Lu, L.-H. (2009). A 0.6 V low-power wide-range delay-locked loop in 0.18 μ. IEEE Microwave and Wireless Components Letters, 19(10), 662–664.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  1. 1.College of Information and Communication EngineeringSungkyunkwan UniversitySuwonKorea

Personalised recommendations