Abstract
This article presents a high-speed, high-linearity 400 × 320 pixel CMOS image sensor with column parallel ADC. The pixel readout circuit is integrated in the 320 columns at one side of the pixel array and all columns consume 16 mW power provided from the 2.5 V power supply. A technique for accelerating conversion speed using two step single slope structure is developed. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11-bit ADC is implemented in 0.25 μm CMOS technology. Moreover, an overall SNR of 63.8 dB can be achieved at 0.5 Msample/s. The power dissipation of all 320 column-parallel ADCs with the peripheral circuits consumes 76 mW.
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Teymouri, M. A high-speed CMOS image sensor with a 11-bit column-parallel A/D converter. Analog Integr Circ Sig Process 74, 279–289 (2013). https://doi.org/10.1007/s10470-012-9911-y
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DOI: https://doi.org/10.1007/s10470-012-9911-y