Skip to main content
SpringerLink
Log in

A sub-1-V, high precision, ultra low-power, process trimmable, resistorless voltage reference with low cost 90-nm standard CMOS technology

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

A low power voltage reference generator operating with a supply voltage ranging from 1.6 to 3.6 V has been implemented in a 90-nm standard CMOS technology. The reference is based on MOSFETs that are biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6 V and at 125°C is 173 nA. It provides a 771 mV voltage reference. A temperature coefficient of 7.5 ppm/°C is achieved at best and 39.5 ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. Several process parameters affect the performance of the proposed voltage reference circuit, so a process adjustment aimed at correcting errors in the reference voltage caused by these variations is dealt with. The total block area is 0.03 mm2.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19

Similar content being viewed by others

References

  1. Bravaix, A., Goguenheim, D., Revil, N., Vincent, E., Varrot, M., & Mortini, P. (1999). Analysis of high temperature effects on performances and hot-carrier degradation in DC/AC stressed 0.35 μm n-MOSFET’s. Microelectronics Reliability, 39(1), 35–44.

    Article  Google Scholar 

  2. Leung, K. N., & Mok, P. K. T. (2002). A sub-1-V 15 ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device. IEEE Journal of Solid-State Circuits, 37, 526–530.

    Article  Google Scholar 

  3. Tanaka, H., Nakagome, Y., Etoh, J., Yamasaki, E., Aoki, M., & Miyazawa, K. (1994). Sub-1V dynamic reference voltage generator for battery-operated DRAMs. IEEE Journal of Solid-State Circuits, 29(4), 448–453.

    Article  Google Scholar 

  4. Vittoz, A., & Neyroud, O. (1979). A low-voltage CMOS bandgap reference. IEEE Journal of Solid-State Circuits, 14(3), 573–577.

    Article  Google Scholar 

  5. Giustolisi, G. et al. (2003). A low-voltage low-power voltage reference based on subthreshold MOSFETs. IEEE Journal of Solid-State Circuits, 38, 151–154.

    Article  Google Scholar 

  6. Vittoz, E., & Fellrath, J. (1977). CMOS analog circuits based on weak inversion operation. IEEE Journal of Solid-State Circuits, SC-12, 224–231.

    Article  Google Scholar 

  7. De Vita, G., & Iannaccone, G. (2005). An ultra-low-power, temperature compensated voltage reference generator. In Proceedings of CICC (pp. 751–754).

  8. Leung, K. N., & Mok, P. K. T. (2003). A CMOS voltage reference based on weighted Vgs for CMOS low-dropout linear regulators. IEEE Journal of Solid-State Circuits, 38(1), 146–150.

    Article  Google Scholar 

  9. Banba, H. et al. (1999). A CMOS bandgap reference circuit with sub-1V operation. IEEE Journal of Solid-State Circuits, 34, 670–674.

    Article  Google Scholar 

  10. Tsividis, Y. (1999). Operation and modeling of the MOS transistor (2nd ed., p. 190). New York, USA: MacGraw Hill.

    Google Scholar 

  11. Taur, Y., & Ning, T. H. (1998). Fundamentals of modern VLSI devices (p. 131). Cambridge: Cambridge University Press.

    Google Scholar 

  12. Oguey, H., & Aebischer, D. (1997). CMOS current reference without resistance. IEEE Journal of Solid-State Circuits, 32(7), 1132–1135.

    Article  Google Scholar 

  13. Camacho-Galeano, E. M., Galup-Montoro, C., & Schneider, M. C. (2005). A 2-nW 1.1-V self-biased current reference in CMOS technology. IEEE Transactions on Circuits and Systems II, 52(2), 333–336.

    Article  Google Scholar 

  14. Swanson, R. M., & Meindl, J. D. (1972). Ion-implanted complementary MOS transistor in low-voltage circuits. IEEE Journal of Solid-State Circuits, SC-7, 146–153.

    Article  Google Scholar 

  15. Nissinen, I., & Sawan, M. (2003). A 900 mV 25 μW High PSRR CMOS voltage reference dedicated to implantable micro-devices. IEEE International Symposium on Circuits and Systems, 1, 373–376.

    Google Scholar 

  16. Hu, Y., & Kostamovaara, J. (2004). A low voltage CMOS constant current voltage reference circuit. IEEE International Symposium on Circuits and Systems, 1, 381–384.

    Google Scholar 

  17. De Vita, G., Iannaccone, G., & Andreani, P. (2006). A 300 nW, 12 ppm/°C voltage reference in a digital 0.35 μmCMOS process. In Symposium on VLSI circuits, digest of technical papers (pp. 81–82). Honolulu, HI.

  18. Arora, N. (1993). MOSFET models for VLSI circuit simulation (p. 221). New York: Springer.

    Book  Google Scholar 

  19. Mizuno, K., Ohta, N., Kitagawa, F., & Nagase, H. (1998). Analog CMOS integrated circuits for high-temperature operation with leakage current compensation. High temperature electronics conferences, HITEC, p. 41.

  20. Razavi, B. (2001). Design of analog CMOS integrated circuits (pp. 463–465). New York: McGraw Hill.

    Google Scholar 

  21. Ueno, K., Hirose, T., Asai, T., & Amemiya, Y. (2009). A 300 nW, 15 ppm/°C, 20 ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs. IEEE Journal of Solid-State Circuits, 44(7), 2047–2054.

    Article  Google Scholar 

  22. De Vita, G., & Iannaccone, G. (2007). A Sub-1-V, 10 ppm/°C, nanopower voltage reference generator. IEEE Journal of Solid-State Circuits, 42(7), 1536–1542.

    Article  Google Scholar 

  23. Ma, H., & Zhou, F. (2009). A sub-1 V 115 nA 0.35 μm CMOS voltage reference for ultra low-power applications. In Proceedings of IEEE of the ASIC, ASICON ‘09. IEEE 8th International Conference on ASIC (pp. 1074–1077).

Download references

Acknowledgments

The author would like to thank STMicroelectronics Rousset, E. Kussener, H. Barthelemy, W. Rahajandraibe, L. Girardeau and Y. Bert for their help, fruitful discussions, and encouragement.

Author information

Authors and Affiliations

  1. STMicroelectronics, Z.I. Rousset-Peynier, B.P.2, 13106, Rousset Cedex, France

    Anass Samir, Ludovic Girardeau & Yannick Bert

  2. Microelectronics Department of the Institute of Materials, Microelectronics and Nanoscience of Provence University (IM2NP), UMR CNRS 6242, Marseille, Toulon, France

    Edith Kussener, Wenceslas Rahajandraibe & Hervé Barthélemy

Authors
  1. Anass Samir
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Edith Kussener
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Wenceslas Rahajandraibe
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Ludovic Girardeau
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Yannick Bert
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Hervé Barthélemy
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Anass Samir.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Samir, A., Kussener, E., Rahajandraibe, W. et al. A sub-1-V, high precision, ultra low-power, process trimmable, resistorless voltage reference with low cost 90-nm standard CMOS technology. Analog Integr Circ Sig Process 73, 693–706 (2012). https://doi.org/10.1007/s10470-012-9852-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-012-9852-5

Keywords

Search

Navigation