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Equalization and pre-emphasis based LVDS transceiver

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Abstract

This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS transmitter by eliminating the use of area consuming passive resistor and capacitor used for close loop stability compensation. A preemphasis technique has been introduced to enhance the transmitter output’s signal quality without significantly increasing the power draw. On the receiver part, an equalization technique has also been introduced to further enhance signal quality, increases data rate and improved jitter with relatively low power consumption. The LVDS transmitter consumes 5.4 mA of current while driving an external 100 ohm resistor with an output voltage swing of 440 mV. The chip consumes an area of 0.044 mm2. This LVDS receiver has an input common mode range from 0.1 to 1.6 V. It consumes 34 mW of power with a maximum data rate of 2 Gbps. It consumes an area of 0.147 mm2 a jitter of 11.74 ps rms. A test chip is implemented using 0.18 μm CMOS process.

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References

  1. Boni, A., et al. (2001) LVDS I/O interface for Gb/s-per pin operation in 0.35 μm CMOS. IEEE Journal of Solid State Circuits, 36, 706–711.

    Article  Google Scholar 

  2. Chen, M., et al. (2005). Low-voltage low-power LVDS driver. IEEE Journal of Solid State Circuits, 40(2), 472–479.

    Article  Google Scholar 

  3. Tajalli, A., Muller, P., & Leblebici, Y. (2009). A slew controlled LVDS output driver circuit in 0.18 μm CMOS Technology. IEEE Journal of Solid-State Circuits, 44, 538–548.

    Google Scholar 

  4. Lin, T., & Payne, A. (2000) Design of a low-voltage, low power, wide-tuning integrated oscillator. In Proceedings of international symposium on circuits and systems, pp. 629–632.

  5. Radelinow, A. G., et al. (2005). Low voltage differential signaling (LVDS) driver with pre-Emphasis. US Patent 6,977,534 B2. December 20, 2005.

  6. IEEE standard for low-voltage differential signals (LVDS) for scalable coherent interface (SCI), 1596.3 SCI-LVDS standard, IEEE Std 1596.3-1996, 1996.

  7. Mandal, G., & Mandal, P. (2004) Low power LVDS transmitter with low common mode variation for 1 Gb/s-per pin operation. In Proceedings of international symposium on circuits and systems, pp. 1120–1123.

  8. Jamasb, S., et al. (2001) A 622 Mhz stand-alone LVDS driver pad in 0.18 μm CMOS. In Proceedings of IEEE Midwest symposium on circuits and systems, pp. 610–613.

  9. Chen, J., et al. (2007) Electrical backplane equalization using programmable analog zeros and folded active inductors. IEEE Transactions on Microwave Theory and Techniques, 55, 1459–1466.

    Article  Google Scholar 

  10. Bratov, V., Binkley, J., Katzman, V., & Chroma, J. (2005). Architecture and implementation of a low-power LVDS output buffer for high-speed applications. IEEE Transactions on Circuits System I: Regular Papers, 53(10), 2101–2108.

    Article  Google Scholar 

  11. Lee, J., et al. (2001) Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections. In Proceedings of IEEE international symposium on circuits and systems, pp. 702–705.

  12. Mandal, G., & Mandal, P. (2005) Low-power LVDS receiver for 1.3 Gbps physical layer (PHY) interface. In Proceedings of IEEE international symposium on circuits and systems, pp. 2180–2183.

  13. Choi, Y. (2006) An 1.4 Gbps/ch LVDS receiver with jitter-boundary-based digital de-skew algorithm. In IEEE solid-state circuits conference, pp. 383–386.

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Acknowledgments

The authors would like to thank Silicon Touch Technology for the support of this project, Jen-Chieh Liu, Yu-Chang Tsai for helping me test the chip, Professor Kuo-Hsing Cheng of NCU for supporting the test equipments, and also thanks to the Chip Implementation Center (CIC), Taiwan for the fabrication of the test chip.

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Authors and Affiliations

  1. Taiwan, Republic of China

    Gilbert A. E. Matig-a & Hong-Yi Huang

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  1. Gilbert A. E. Matig-a
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  2. Hong-Yi Huang
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Correspondence to Hong-Yi Huang.

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Matig-a, G.A.E., Huang, HY. Equalization and pre-emphasis based LVDS transceiver. Analog Integr Circ Sig Process 75, 109–123 (2013). https://doi.org/10.1007/s10470-012-0021-7

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  • DOI: https://doi.org/10.1007/s10470-012-0021-7

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