Phase-margin enhancement technique for recycling folded cascode amplifier
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A novel circuit technique for enhancing the phase-margin of the recycling folded cascode amplifier is presented. Compared to the conventional recycling folded cascade, using a high-speed current mirror, the proposed amplifier offers the advantage of cancellation of the first non-dominant pole, allowing the phase-margin to be enhanced without affecting the bandwidth. The proposed amplifier was implemented in CSMC standard 0.18 μm CMOS process. Simulation results show that the phase-margin enhancement of 20° is achieved without limiting the bandwidth.
KeywordsPhase-margin enhancement Recycling folded cascode amplifier High-speed current mirror
This work is supported by the NSFC (Grant No. 11227202).
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