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A 54.2 μW 5 MSps 9-bit ultra-low energy analog-to-digital converter in 180 nm technology

Analog Integrated Circuits and Signal Processing volume 72, pages 37–46 (2012)Cite this article

Abstract

This paper aims to address the growing need for ultra-low power analog-to-digital converters (ADC). For this purpose, we pushed the limitations of conventional successive approximation register ADCs through the use of deep voltage scaling, a novel iterative precharging scheme, and topological improvements over recent works. From the simulations results we achieve a figure of merit of 31 fJ per conversion step, with an 8.45 effective number of bits, working at 5 MSps.

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Authors and Affiliations

  1. Universidade Federal de Santa Maria (UFSM), Santa Maria, Brazil

    Taimur Gibran Rabuske & Cesar Ramos Rodrigues

  2. Michigan Technological University (Michigan Tech), Houghton, MI, 49931, USA

    Saeid Nooshabadi

Authors
  1. Taimur Gibran Rabuske
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  2. Saeid Nooshabadi
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  3. Cesar Ramos Rodrigues
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Correspondence to Saeid Nooshabadi.

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Rabuske, T.G., Nooshabadi, S. & Rodrigues, C.R. A 54.2 μW 5 MSps 9-bit ultra-low energy analog-to-digital converter in 180 nm technology. Analog Integr Circ Sig Process 72, 37–46 (2012). https://doi.org/10.1007/s10470-011-9821-4

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  • DOI: https://doi.org/10.1007/s10470-011-9821-4

Keywords

  • SAR ADC
  • Ultra-low power
  • Ultra-low energy
  • Step-wise
  • Charge sharing

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