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Complexity analysis of software defined DVB-T2 physical layer


The second generation terrestrial TV broadcasting standard from the digital video broadcasting (DVB) project, DVB-T2, has recently been standardized. In this article we perform a complexity analysis of our software defined implementation of the modulator/demodulator parts of a DVB-T2 transmitter and receiver. First we describe the various stages of a DVB-T2 modulator and demodulator, as well as how they have been implemented in our system. We then perform an analysis of the computational complexity of each signal processing block. The complexity analysis is performed in order to identify the blocks that are not feasible to run in realtime on a general purpose processor. Furthermore, we discuss implementing these computationally heavy blocks on other architectures, such as GPUs (graphics processing units) and FPGAs (field-programmable gate arrays), that would still allow them to be implemented in software and thus be easily reconfigurable.

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  1. The "combined" throughput figure was achieved by adding the measured execution times of all blocks in the group, and calculating the throughput as described earlier for one block.

  2. BCH decoding was not actually performed. We do, however, know exactly how many bits a BCH decoder would be able to correct, which is sufficient for simulating the performance of the BCH decoder.


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Correspondence to Stefan Grönroos.

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Grönroos, S., Nybom, K. & Björkqvist, J. Complexity analysis of software defined DVB-T2 physical layer. Analog Integr Circ Sig Process 69, 131–142 (2011).

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  • DVB-T2
  • SDR
  • CUDA
  • x86