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A fractional spur suppression technique in the fractional-N frequency synthesizer

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Abstract

A fractional spur suppression technique is presented based on the principle of spur generation, which makes the phase between the divider output and the reference be permanently coherent like integer-N frequency synthesizer, so a real lock is achieved. The spurious tones are strongly reduced without sacrificing the PLL bandwidth. The detailed scheme and corresponding key building blocks are deeply discussed. A 1.9 GHz frequency synthesizer with a 100 kHz bandwidth is implemented with the proposed way. SpectreVerilog simulation results show that the technique can reduce over 10 dBc/Hz spurious tones. So it is suitable for high spectral purity frequency synthesizer.

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Acknowledgment

This research was partly supported by the National Science Foundation of China (No. 60475018, No. 60372021) and National Key Basic Research and Development Program (No. G2000036508).

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Authors and Affiliations

  1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

    Shui-long Huang & Hai-ying Zhang

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  1. Shui-long Huang
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  2. Hai-ying Zhang
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Correspondence to Shui-long Huang.

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Huang, Sl., Zhang, Hy. A fractional spur suppression technique in the fractional-N frequency synthesizer. Analog Integr Circ Sig Process 66, 455–458 (2011). https://doi.org/10.1007/s10470-010-9565-6

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  • DOI: https://doi.org/10.1007/s10470-010-9565-6

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