Skip to main content
Log in

An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

An 5.1 μW, 1.8 V, 8-bit, successive approximation (SAR) analog-to-digital converter (ADC) using 10 kHz clock was designed and fabricated in a 0.18 μm CMOS technology for passive UHF radio frequency identification (RFID) applications. The ADC utilises a resistive digital to analog converter (DAC). The ADC can operate with low power consumption. The proposed comparator with cascode active load can offer large gain and can operate at a low supply voltage. The measured total power consumption is 5.1 μW at a 10 kHz input clock with a 1.8 V single supply, and 0.5 μW with 970 mV supply.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19

Similar content being viewed by others

Abbreviations

ADC:

Analog-to-digital converter

A VO :

Open-loop gain

BW −3dB :

−3 dB bandwidth

DAC:

Digital-to-analog converter

DC:

Direct current

DNL:

Differential non linearity

ENOB:

Effective number of bits

IC:

Integrated circuit

INL:

Integral non linearity

LSB:

Least significant bit

MOS:

Metal oxide semiconductor

MOSFET:

MOS field-effect (transistor)

MSB:

Most significant bit

NMOS:

Negative MOS (transistor)

NOB:

Number of bits

PM:

Phase margin

PMOS:

Positive MOS (transistor)

PSD:

Power spectral density

RF:

Radio frequency

RFID:

Radio frequency identification

RMS:

Root-mean-square

SC:

Switching-capacitor

SFDR:

Spurious free dynamic range

UHF:

Ultra high frequency

References

  1. Muthusamy, K., Hui, Teo, T., & Yong Ping, X. (2009). A 1-V 32-W 13-bit CMOS sigma-delta A/D converter for biomedical applications. In IEEE 8th international conference on ASIC, ASICON ’09, pp. 207–210.

  2. Jiaxin, J., Wanrong, Z., Haolin, D., Yanfeng, J., & Yamin, Z. (2009). New architecture of low voltage sigma-delta ADC. In IEEE 8th international conference on ASIC, ASICON ’09, pp. 203–206.

  3. Steyaert, M., Peluso, V., Bastos, J., Kinget, P., & Sansen, W. (1997). Custom analog low power design: The problem of low voltage and mismatch. In Proceedings of the IEEE 1997 custom integrated circuits conference, pp. 285–292.

  4. Safi-Harb, M., & Roberts, G. W. (2005). Low power delta-sigma modulator for ADSL applications in a low-voltage CMOS technology. IEEE Transactions on Circuits and Systems I: Regular Papers, 52(10), 2075–2089.

    Article  Google Scholar 

  5. Kijima, M., Ito, K., Kamei, K., & Tsukamoto, S. (2009). A 6b 3GS/s flash ADC with background calibration. In IEEE custom integrated circuits conference, 2009, CICC ’09, pp. 283–286.

  6. Cho, Y.-J., Lee, K.-H., Choi, H.-C., Kim, Y.-J., Moon, K.-J., Lee, S.-H., Hyun, S.-B., & Park, S.-S. (2006). A dual-channel 6b 1GS/s 0.18 um CMOS ADC for ultra wide-band communication systems. In IEEE Asia Pacific conference on circuits and systems, 2006, APCCAS 2006, pp. 339–342.

  7. Chen, P.-H., & Peckerar, M. (2007). A 5-bit interpolating flash ADC in 0.13-m SiGe BiCMOS. In IEEE international conference on integrated circuit design and technology, 2007, ICICDT ’07, pp. 1–3.

  8. Po-Hsin, C., & Peckerar, M. (2007). A 5-bit interpolating flash ADC in 0.13-m SiGe BiCMOS. In Integrated circuit design and technology, 2007, ICICDT ’07, IEEE international conference, pp. 1–3.

  9. Lee, H.-Y., Wang, I.-H., & Liu, S.-I. (2007). A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS. In IEEE international SOC conference, 2007, pp. 11–14.

  10. Walden, R. H. (1999). Analog-to-digital converter survey and analysis. IEEE Journal on Selected Areus in Communications, 17(4), 539–550.

    Article  Google Scholar 

  11. Neubauer, H., Desel, T., & Hauer, H. (2001). A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 m CMOS using self calibration and low power techniques. In The 8th IEEE international conference on electronics, circuits and systems, 2001, ICECS 2001, 2–5 September 2001, Vol. 2, pp. 859–862.

  12. Rivetti, A., Anelli, G., Anghinolfi, F., Mazza, G., & Rotondo, F. (2000). A low-power 10 bit ADC in a 0.25 m CMOS: Design considerations and test results. In 2000 IEEE nuclear science symposium conference record, 15–20 October 2000, Vol. 2, pp. 9/15–9/18.

  13. Hong, H.-C., & Lee, G.-M. (2007). A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC. IEEE Journal of Solid-State Circuits, 42(10), 2161–2168.

    Article  Google Scholar 

  14. Kim, H., Min, Y. J., Kim, Y., & Kim, S. (2008). A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array. In IEEE international conference on electron devices and solid-state circuits, 2008, EDSSC 2008, 8–10 December 2008, pp. 1–4.

  15. Abdelhalim, K., MacEachern, L., & Mahmoud, S. (2006). A nanowatt ADC for ultra low power applications. In IEEE international symposium on circuits and systems, 2006, ISCAS 2006. Proceedings, p. 4.

  16. Ravezzi, L., Stoppa, D., & Dalla Betta, G.-F. (1998). Current-mode A/D converter. Electronics Letters, 34(7), 615–616.

    Article  Google Scholar 

  17. Sauerbrey, J., Schmitt-Landsiedel, D., & Thewes, R. (2002). A 0.5V, 1 uW successive approximation ADC, ESSIRC 2002. In Proceedings of the European solid-state circuit conference, Firenze, Italy, 24–26 Sebtember 2002, pp. 247–250.

  18. Agarwal, A., Kim, Y. B., & Sonkusale, S. (2005). Low power current mode ADC for CMOS sensor IC. In IEEE international symposium on circuits and systems, ISCAS 2005, 23–26 May 2005, Vol. 1, pp. 584–587.

  19. Quinn, P., & Pribytko, M. (2003). Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 m CMOS. In Proceedings of the IEEE 2003 custom integrated circuits conference, pp. 425–428.

  20. Li, J., Ahn, G.-C., Chang, D.-Y., & Moon, U.-K. (2005). A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR. IEEE Journal of Solid-State Circuits, 40(4), 960–969.

    Article  Google Scholar 

  21. Kim, M. G., Hanumolu, P. K., & Moon, U.-K. (2009). A 10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme. IEEE Journal of Solid-State Circuits, 44(9), 2348–2355.

    Article  Google Scholar 

  22. Järvinen, J. A. M., Saukoski, M., & Halonen, K. (2006). A 12-bit 32 μW ratio-independent algorithmic ADC. In Symposium on VLSI circuits, 2006. Digest of Technical Papers, pp. 47–48.

  23. Agarwal, A., Kim, Y. B., & Sonkusale, S. (2005). Low power current mode ADC for CMOS sensor IC. In IEEE international symposium on circuits and systems, 2005, ISCAS 2005, Vol. 1, pp. 584–587.

  24. Allen, P. E., & Holmberg, D. R. (1987). CMOS analog circuit design (p. 701). Philadelphia: Saunders College Publishing.

    Google Scholar 

  25. Gregorian, R., & Temes, G. C. (1986). Analog MOS integrated circuits for signal processing (p. 598). New York: Wiley.

    Google Scholar 

  26. Razavi, B. (1995). Principles of data conversion system design (p. 251). New York: IEEE Press.

    Google Scholar 

  27. Marjonen, J., Alaoja, R., Ronkainen, H., & Åberg, M. (2006). Low power successive approximation A/D converter for passive RFID tag sensor. In BEC 2006—proceedings of the 10th biennial baltic electronics conference, Tallinn University of Technology, Tallinn, Estonia, 2–4 October 2006, pp. 107–110.

  28. El Mustapha Ait Yakoub, M., Sawan, M., & Thibeault, C. (2009). A neuromimetic ultra low-power ADC for bio-sensing applications. In Joint IEEE north-east workshop on circuits and systems and TAISA conference, NEWCAS-TAISA ’09, June 28–July 1, 2009, pp. 1–4.

  29. Allier, E., Goulier, J., Sicard, G., Dezzani, A., Andre, E., & Renaudin, M. (2005). A 120 nm low power asynchronous ADC. In Proceedings of the 2005 international symposium on low power electronics and design, ISLPED ’05, 8–10 August 2005, pp. 60–65.

  30. Trojer, M., Pribyl, W., & Garcia-Gonzalez, J.-M. (2009). A 10bit 1.1V 130MS/s 0.125mm2 pipeline ADC for flat-panel display applications in 65nm CMOS. In Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D., pp. 4–7.

  31. Honda, K., Furuta, M., & Kawahito, S. (2007). A low-power low-voltage 10-bit 100-MSample/s pipeline A/D converter using capacitance coupling techniques. IEEE Journal of Solid-State Circuits, 42(4), 757–765.

    Article  Google Scholar 

  32. Adeniran, O. A., & Demosthenous, A. (2005). Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs. In Proceedings of the 2005 European conference on circuit theory and sesign, Vol. 2, pp. II/55–II/58.

  33. Dyer, K., Fu, D., Lewis, S., & Hurst, P. (1998). Analog background calibration of a 10 b 40 Msample/s parallel pipelined ADC. In IEEE international solid-state circuits conference, 1998. Digest of Technical Papers, pp. 142–143, 427.

  34. Cho, S. H., Ock, S., Lee, S.-H., & Lee, J.-S. (2005). A low power pipelined analog-to-digital converter using series sampling capacitors. In IEEE international symposium on circuits and systems, 2005, ISCAS 2005, 23–26 May 2005, Vol. 6, pp. 6178–6181.

Download references

Acknowledgments

This work is being performed within the framework of the IntelliSense RFID project under the Nordic research programme NORDITE funded by VINNOVA (Sweden), the Research Council of Norway (Norway), and Tekes (Finland). The responsible author would like to thank professors Pekka Kuivalainen, at TKK, and Markku Åberg, at VTT, for several inspiring and interesting research subject during the past 15 years at VTT, and wishes all the best for the future to all his former colleagues.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to J. Marjonen.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Marjonen, J., Vermesan, O. & Rustad, H. An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities. Analog Integr Circ Sig Process 66, 389–405 (2011). https://doi.org/10.1007/s10470-010-9527-z

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-010-9527-z

Keywords

Navigation