Abstract
An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 μm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 × 0.9 mm2 without I/O pads.
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Acknowledgments
The authors would like to thank the reviewers for their valuable suggestions. The authors would also like to thank the Chip Implementation Center of Taiwan for the technical supporting and IC implementation. This work was supported by the National Science Council of Taiwan under Grant NSC 96-2221-E-027-130.
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Hwang, YS., Huang, PH., Hwang, BH. et al. An efficient power reduction technique for CMOS flash analog-to-digital converters. Analog Integr Circ Sig Process 61, 271–278 (2009). https://doi.org/10.1007/s10470-009-9309-7
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DOI: https://doi.org/10.1007/s10470-009-9309-7