Abstract
This paper proposes a 10 b 120 MS/s CMOS ADC with a PVT-insensitive current reference. The designed current reference shows a mean temperature drift of 35.2 ppm/°C in the temperature range from −25 to 100°C and a supply rejection of 1.1%/V between 1.6 and 2.0 V. The prototype ADC fabricated in a 0.18 μm 1P6M CMOS technology demonstrates a measured DNL and INL of 0.18LSB and 0.53LSB with a maximum SNDR and SFDR of 53 and 68 dB at 120 MS/s. The ADC with an active chip area of 1.8 mm2 consumes 108 mW at 120 MS/s and 1.8 V while the proposed on-chip current reference consumes 0.35 mW with a die area of 0.02 mm2.
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This work was partly supported by the IDEC of KAIST, Korea.
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Choi, HC., Kim, YJ., Kim, WJ. et al. A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference. Analog Integr Circ Sig Process 58, 115–121 (2009). https://doi.org/10.1007/s10470-008-9231-4
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DOI: https://doi.org/10.1007/s10470-008-9231-4