Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI

  • Amir H. Ajami
  • Kaustav Banerjee
  • Massoud Pedram


This paper presents a detailed scaling analysis of the power supply distribution network voltage drop in DSM technologies. The effects of chip temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the voltage drop effect in the power/ground (P/G) distribution network increases rapidly with technology scaling, and that using well-known countermeasures such as wire-sizing and/or decoupling capacitor insertion which are typically used in the present design methodologies may be insufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power supply lines of switching devices in a clock distribution network can introduce significant amount of skew which in turn degrades the signal integrity.


barrier thickness clock skew de-coupling capacitance power distribution network surface scattering technology scaling thermal gradient voltage drop 


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Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  • Amir H. Ajami
    • 1
  • Kaustav Banerjee
    • 2
  • Massoud Pedram
    • 3
  1. 1.Magma Design AutomationSanta Clara
  2. 2.ECE Dept., 4151 Eng IUniv. of California at Santa BarbaraSanta Barbara
  3. 3.EE-Systems Dept., 3740 McClintock AveUniv. of Southern CaliforniaLos Angeles

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