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Error reduction of SRAM-based physically unclonable function for chip authentication

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Abstract

SRAM-based physically unclonable function (PUF) is an attractive security primitive for cryptographic protocol and security architecture because SRAM itself is one of the most widely used embedded memories. In terms of robustness, however, there is a weakness for SRAM PUF owing to a bit error; thus, a method must be explored to reduce this error. In this work, a novel hardware chip to characterize cell-to-cell entropy is demonstrated for robust SRAM based PUF by implementation of a screening test to filter out poor cells. We design a chip with a power controller, circuits for error correction coding, a SRAM array and central processing unit. Then it was fabricated by a foundry service. We also propose a procedure to suppress the bit error by use of a screening test, which is based on SRAM cells possessing their own entropy. Through the screening test, the bit error rate (BER) is reduced to below \({10}^{-6}\), which is much smaller than the BER of 0.05 in previous reports, i.e., the robustness is notably improved. Moreover, this robustness was evaluated in terms of an error correction code (ECC) failure rate and temperature after the screening test. SRAM-based PUF with enhanced robustness can contribute to implementing a security protocol and architecture for chip authentication.

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Data availability statments

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

References

  1. Pu, C., Choo, K.-K.R.: Lightweight Sybil attack detection in IoT based on bloom filter and physical unclonable function. Comput. Secur. 113, 102541 (2022)

    Article  Google Scholar 

  2. Ahmim, I., Ghoualmi-Zine, N., Ahmim, A., Ahmim, M.: Security analysis on “Three-factor authentication protocol using physical unclonable function for IoV. Int. J. Inf. Secur. 21, 1019–1026 (2022)

    Article  Google Scholar 

  3. Melki, R., Noura, H.N., Chehab, A.: Lightweight multi-factor mutual authentication protocol for IoT devices. Int. J. Inf. Secur. 19, 679–694 (2020)

    Article  Google Scholar 

  4. Abdussami, M., Amin, R., Vollala, S.: LASSI: a lightweight authenticated key agreement protocol for fog-enabled IoT deployment. Int. J. Inf. Secur. 21(6), 1373–1387

  5. Aniello, L., Halak, B., Chai, P., Dhall, R., Mihalea, M., Wilczynski, A.: Anti-BlUFf: towards counterfeit mitigation in IC supply chains using blockchain and PUF. Int. J. Inf. Secur. 20, 445–460 (2021)

    Article  Google Scholar 

  6. Shamsoshoara, A., Korenda, A., Afghah, F., Zeadally, S.: A survey on physical unclonable function (PUF)-based security solutions for Internet of Things. Comput. Netw. 183(24), 107593 (2020)

    Article  Google Scholar 

  7. Fatemeh, T., Karimian, N., Yan, W., Chandy, J.A.: DRAM-based intrinsic physically unclonable functions for system-level security and authentication. IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 25(3), 1085–1097 (2016)

    Google Scholar 

  8. Yu, J.-M., Yun, G.-J., Kim, M.-S., Han, J.-K., Kim, D.-J., Choi, Y.-K.: A poly-crystalline silicon nanowire transistor with independently controlled double-gate for physically unclonable function by multi-states and self-destruction. Adv. Electron. Mater. 7(5), 2000989 (2021)

    Article  Google Scholar 

  9. Kim, M.-S., Moon, D.-I., Yoo, S.-K., Lee, S.-H., Choi, Y.-K.: Investigation of physically unclonable functions using flash memory for integrated circuit authentication. IEEE Trans. Nanotechnol. 14(2), 384–389 (2015)

    Article  Google Scholar 

  10. Dodo, S.B., Bishnoi, R., Nair, S.M., Tahoori, M.B.: A spintronics memory PUF for resilience against cloning counterfeit. IEEE Trans. Very Large Scale Integr. VLSI Syst. 27(11), 2511–2522 (2019)

    Article  Google Scholar 

  11. Li, S., Zhang, T., Yu, B., He, K.: A provably secure and practical PUF-based end-to-end mutual authentication and key exchange protocol for IoT. IEEE Sens. J. 21(4), 5487–5501 (2021)

    Article  Google Scholar 

  12. Usmani, M.A., Keshavarz, S., Matthews, E., Shannon, L., Tessier, R., Holcomb, D.E.: Efficient PUF-based key generation in FPGAs using per-device configuration. IEEE Trans. Very Large Scale Integr. VLSI Syst. 27(2), 364–375 (2018)

    Article  Google Scholar 

  13. Chen, B., Ignatenko, T., Willems, F.M.J., Maes, R., Sluis, E., Selimis, G.: A robust SRAM-PUF key generation scheme based on polar codes. In: 2017 Global Communications Conference, pp. 1–6 (2017)

  14. Holcomb, D.E., Burleson, W.P., Fu, K.: Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. 58(9), 1198–1210 (2008)

    Article  MathSciNet  MATH  Google Scholar 

  15. Cortez, M., Hamdioui, S., Kaichouhi, A., Leest, V., Maes, R., Schrijen, G.-J.: Intelligent voltage ramp-up time adaptation for temperature noise reduction on memory-based PUF systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7), 1162–1175 (2015)

    Article  Google Scholar 

  16. Baturone, I., Prada-Delgado, M.A., Eiroa, S.: Improved generation of identifiers, secret keys, and random numbers from SRAMs. IEEE Trans. Inf. Forensics Secur. 10(12), 2653–2668 (2015)

    Article  Google Scholar 

  17. Shifman, Y., Miller, A., Keren, O., Weizman, Y., Shor, J.: An SRAM-based PUF with a capacitive digital preselection for a 1E–9 key error probability. IEEE Trans. Circuits Syst. I Regul. Pap. 67(12), 4855–4868 (2020)

    Article  Google Scholar 

  18. Patil, V.C., Vijayakumar, A., Holcomb, D.E., Kundu, S.: Improving reliability of weak PUFs via circuit techniques to enhance mismatch. In: 2017 IEEE International Symposium on Hardware Oriented Security and Trust, pp. 146–150 (2017)

  19. Maes, R., Leest, V.: Countering the effects of silicon aging on SRAM PUFs. In: 2014 IEEE International Symposium on Hardware Oriented Security and Trust, pp. 148–153 (2014)

  20. Mispan, M.S., Duan, S., Halak, B., Zwolinski, M.: A reliable PUF in a dual function SRAM. Integration 68, 12–21 (2019)

    Article  Google Scholar 

  21. Bhargava, M., Mai, K.: A high reliability PUF using hot carrier injection based response reinforcement. In: 2013 International Conference on Cryptographic Hardware and Embedded Systems, pp. 90–106 (2013)

  22. Maes, R.: An accurate probabilistic reliability model for silicon PUFs. In: 2013 International Conference on Cryptographic Hardware and Embedded Systems, pp. 73–89 (2013)

  23. Delvaux, J., Gu, D., Schellekens, D., Verbauwhede, I.: Helper data algorithms for PUF-based key generation: overview and analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6), 889–902 (2014)

    Article  Google Scholar 

  24. Patil, A.S., Hazma, R., Hassan, A., Jiang, N., Yan, H., Li, J.: Efficient privacy-preserving authentication protocol using PUFs with blockchain smart contracts. Comput. Secur. 97, 101958 (2020)

    Article  Google Scholar 

  25. Strieder, E., Frisch, C., Pehl, M.: Machine learning of physical unclonable functions using helper data. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(2), 1–36 (2021)

    Google Scholar 

  26. Kusters, L., Ignatenko, T., Willems, F.M.J., Maes, R., Sluis, E., Selimis, G.: Security of helper data schemes for SRAM-PUF in multiple enrollment scenarios. In: 2017 IEEE International Symposium on Information Theory, pp. 1803–1807 (2017)

  27. Sarangi, S., Banerjee, S.: Efficient hardware implementation of encoder and decoder for Golay code. IEEE Trans. Very Large Scale Integr. VLSI Syst. 23(9), 1965–1968 (2014)

    Article  Google Scholar 

  28. Jose, A., Sujithamol, S.: FPGA implementation of encoder and decoder for Golay code. In: 2017 ccc, pp. 892–896 (2017)

  29. Maity, R.K., Tripathi, S., Samanta, J., Bhaumik, J.: Lower complexity error location detection block of adjacent error correcting decoder for SRAMs. IET Comput. Digit. Tech. 14(5), 210–216 (2020)

    Article  Google Scholar 

  30. Ho, W.-G., Chong, K.-S., Kim, T.T.-H., Gwee, B.-H.: A secure data-toggling SRAM for confidential data protection. IEEE Trans. Circ. Syst. I Regular Papers 66(11), 4186–4199 (2019)

    Article  Google Scholar 

  31. Benfica, J., Green, B., Porcher, B.C., Poehls, L.B., Vargas, F., Medina, N.H., Added, N., Aguiar, V.A.P., Macchione, E.L.A., Aguirre, F., Silveira, M.A.G., Perez, M., Haro, M.S., Sidelnik, I., Blostein, J., Lipovetzky, J., Bezerra, E.A.: Analysis of SRAM-based FPGA SEU sensitivity to combined EMI and TID-imprinted effects. IEEE Trans. Nucl. Sci. 63(2), 1294–1300 (2016)

    Article  Google Scholar 

  32. Holcomb, D.E., Fu, K.: Bitline PUF: building native challenge-response PUF capability into any SRAM. In: 2014 IEEE International Workshop on Cryptographic Hardware and Embedded Systems, pp. 510–526 (2014)

  33. Zhang, L., Chang, C.-H., Kong, Z.H., Liu, C.Q.: Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes. In: IEEE International Symposium on Circuits and Systems, pp. 1410–1413 (2015)

  34. Takeuchi, K., Fukai, T., Tsunomura, T., Putra, A.T., Nishida, A., Kamohara, S., Hiramoto, T.: Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies. In: IEEE International Electron Devices Meeting, pp. 467–470 (2007)

  35. Rao, R., DasGupta, N., DasGupta, A.: Study of random dopant fluctuation effects in FD-SOI MOSFET using analytical threshold voltage model. IEEE Trans. Device Mater. Reliab. 10(2), 247–253 (2010)

    Article  Google Scholar 

  36. Razavipour, G., Afzali-Kusha, A., Pedram, M.: Design and analysis of two low-power SRAM cell structures. IEEE Trans. Very Large Scale Integr. VLSI Syst. 17(10), 1551–1555 (2009)

    Article  Google Scholar 

  37. Alorda, B., Torrens, G., Bota, S., Segura, J.: Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells. Microelectron. Reliab. 54(11), 2613–2620 (2014)

    Article  Google Scholar 

  38. Rezaei, E., Donato, M., Patterson, W.R., Zaslavsky, A., Bahar, R.I.: Fundamental thermal limits on data retention in low-voltage CMOS latches and SRAM. IEEE Trans. Device Mater. Reliab. 20(3), 488–497 (2020)

    Article  Google Scholar 

  39. Shakir, T., Sachdev, M.: A word-line boost driver design for low operating voltage 6T-SRAMs. In: 2012 IEEE 55th International Midwest Symposium on Circuits and Systems , pp. 33–36 (2012)

  40. Katzenbeisser, S., Kocabas, U., RoZIC, V., Sadeghi, A.-R., Verbauwhede, I., Wachsmann, C.: PUFs: Myth, fact or busted? A security evaluation of physically unclonable functions (PUFs) cast in silicon. In: International Workshop on Cryptographic Hardware and Embedded Systems, pp. 283–301 (2012)

  41. Gu, C., Liu, W., Hanley, N., Hesselbarth, R., O’Neill, M.: A theoretical model to link uniqueness and min-entropy for PUF evaluations. IEEE Trans. Comput. 68(2), 287–293 (2018)

    Article  MathSciNet  MATH  Google Scholar 

  42. Anagnostopoulos, N.A., Arul, T., Rosenstihl, M., Schaller, A., Gabmeyer, S., Katzenbeisser, S.: Low-temperature data remanence attacks against intrinsic SRAM PUFs. In: 2018 21st Euromicro Conference on Digital System Design, pp. 581–585 (2018)

  43. Cakir, C., Bhargava, M., Mai, K.: 6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS. In: 2012 IEEE Custom Integrated Circuits Conference, pp. 1–4 (2012)

  44. Delvaux, J.: Machine-learning attacks on polyPUFs, OB-PUFs, RPUFs, LHS-PUFs, and PUF-FSMs. IEEE Trans. Inf. Forensics Secur. 14(8), 2043–2058 (2019)

    Article  Google Scholar 

  45. Gope, P., Millwood, W., Sikdar, B.: A scalable protocol level approach to prevent machine learning attacks on physically unclonable function based authentication mechanisms for internet of medical things. IEEE Trans. Industr. Inf. 18(3), 1971–1980 (2022)

    Article  Google Scholar 

  46. Bhargava, M., Mai, K.: An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. In: 2014 Design, Automation & Test in Europe Conference & Exhibition, pp. 1–6 (2014)

  47. Chen, B., Ignatenko, T., Willems, F.M.J., Maes, R., Sluis, E., Selimis, G.: A robust SRAM-PUF key generation scheme based on polar codes. In: 2017 IEEE Global Communications Conference, pp. 1–6 (2017)

  48. Yan, W., Tehranipoor, F., Chandy, J.A.: PUF-based fuzzy authentication without error correcting codes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9), 1445–1457 (2016)

    Article  Google Scholar 

  49. Pittalia, P.P.: A comparative study of hash algorithms in cryptography. Int. J. Comput. Sci. Mob. Computing. 8(6), 147–152 (2019)

  50. Wong, M.M., Haj-Yahya, J., Sau, S., Chattopadhyay, A.: A new high throughput and area efficient SHA-3 implementation. In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2018)

  51. Rukhin, A., Soto, J., Nechvatal, J., Smid, M., Barker, E., Leigh, S., Dray, J.: NIST special publication 800-22 revision 1a: A statistical test suite for random and pseudorandom number generators for cryptographic applications. NIST US Department of Commerce (2010)

  52. Wong, M.M., Haj-Yahya, J., Sau, S., Chattopadhyay, A.: A new high throughput and area efficient SHA-3 implementation. In: 2018 IEEE International Symposium on Circuits and Systems, pp. 1–5 (2018)

  53. Kim, M.-S., Tcho, I.-W., Park, S.-J., Choi, Y.-K.: Random number generator with a chaotic wind-driven triboelectric energy harvester. Nano Energy 78, 105275 (2020)

    Article  Google Scholar 

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Acknowledgements

This work was supported in part by the National Research Foundation (NRF) of the Republic of Korea, under Grant 2018R1A2A3075302 and Grant 2020M3F3A2A01082592, and in part by the Soonchunhyang University Research Fund.

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Authors and Affiliations

  1. School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Republic of Korea

    Moon-Seok Kim, Ji-Man Yu, Il-Woong Tcho & Yang-Kyu Choi

  2. The attached Institute of ETRI, Yuseong-gu, Daejeon, 34141, Republic of Korea

    Moon-Seok Kim, Sang-Kyung Yoo & Bong-Soo Lee

  3. Department of Electronic Engineering, Soonchunhyang University, Asan, 31538, Republic of Korea

    Moon-Seok Kim

  4. Department of Electrical Engineering and Convergence Engineering for Intelligent Drone, Sejong University, Seoul, 05006, Republic of Korea

    Sungho Kim

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Contributions

M-SK contributed to conceptualization, methodology, investigation, and main manuscript text. SK contributed to software development. S-KY contributed to formal analysis and visualization. B-SL contributed to ASIC development. J-MY contributed to data curation. I-WTS contributed to methodology. Y-KC contributed to review and editing main manuscript and project administration. All authors reviewed manuscript.

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Correspondence to Yang-Kyu Choi.

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Kim, MS., Kim, S., Yoo, SK. et al. Error reduction of SRAM-based physically unclonable function for chip authentication. Int. J. Inf. Secur. 22, 1087–1098 (2023). https://doi.org/10.1007/s10207-023-00668-0

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