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A loop acceleration technique to speed up verification of automatically generated plans

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Abstract

The CIRCA planning system automatically creates reactive plans and uses formal verification techniques to prove that those plans will preserve system safety. CIRCA’s timed automata verification system is highly efficient, yet can display pathologically bad behavior when reasoning about reaction loops, a particular form of interacting cycles of states. In this paper, we describe a loop acceleration technique that recognizes these state-space structures during the verification process and bypasses the process of expanding an arbitrarily large cycle of states, effectively compressing loops of arbitrary size into a compact, finite set of states. The resulting performance improvement can be very dramatic: in domains where tight loops of short-duration transitions interact with long-duration transitions, our new loop acceleration methods can reduce verification time (and hence planning time) from hours to below a second.

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Notes

  1. Labels are used in parallel composition of timed automata, which we do not use here.

  2. CIRCA actually supports non-deterministic transitions that have multiple different effect feature assignments, but for this presentation we ignore that complication.

  3. Because of the simplicity of the feature-value representation, for any two assignments, \(\mathcal{A}_{1}\) and \(\mathcal{A}_{2}\), \(\mathcal{A}_{1} \models \mathcal{A}_{2}\) iff \(\mathcal{A}_{1} \supseteq \mathcal{A}_{2}\).

  4. Source for the evaluation domain is available at http://www.musliner.com/david/papers/sttt2013loopacceldata.html.

  5. Timing information was obtained by running on a Linux computer with an Intel Duo2 dual core 2.4GHz CPU (4,800 BogoMips) and 6 gigabytes of memory.

  6. Note that, while we use the term “threat,” the pattern is actually more general—any case where the controller must service an outside process that is time-pressured exhibits the same pattern.

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Acknowledgments

This article was supported by Office of Naval Research contract N0014-10-1-0188 via Carnegie Mellon University subaward number 1140185-240250 and Air Force Office of Scientific Research contract FA9550-12-1-0146 via Carnegie Mellon University subaward number 1150105-284227. This paper does not represent the official position or opinions of the Office of Naval Research, the Air Force Office of Scientific Research, or Carnegie Mellon University. Thanks to Ed Koeller for collecting supporting images and data. Thanks to our reviewers for many helpful questions, suggestions, and corrections.

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  1. SIFT, LLC, Minneapolis, MN, USA

    Robert P. Goldman, Michael J. S. Pelican & David J. Musliner

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  1. Robert P. Goldman
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  2. Michael J. S. Pelican
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  3. David J. Musliner
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Correspondence to Michael J. S. Pelican.

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Goldman, R.P., Pelican, M.J.S. & Musliner, D.J. A loop acceleration technique to speed up verification of automatically generated plans. Int J Softw Tools Technol Transfer 16, 13–29 (2014). https://doi.org/10.1007/s10009-013-0284-z

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