FPGA friendly NoC simulation acceleration framework employing the hard blocks

Abstract

A major role is played by Modeling and Simulation platforms in development of a new Network-on-Chip (NoC) architecture. The cycle accurate software simulators tend to become slow when simulating thousands of cores on a single chip. FPGAs have become the vehicle for simulation acceleration due to the properties of parallelism. Most of the state-of-the-art FPGA based NoC simulators utilize soft logic only for modeling the NoCs, leaving out the hard blocks to be unutilized. In this work, the FIFO Buffer and Crossbar switch functionalities of the NoC router have been embedded in the Block RAM (BRAMs) and the DSP48E1 slices with large multiplexer respectively. Employing the proposed techniques of mapping the NoC router components on the FPGA hard blocks, an NoC simulation acceleration framework based on the FPGA is presented in this work. A huge reduction in the use of the Configurable Logic Blocks (CLBs) has been observed when the FIFO buffer and Crossbar components of the NoC topology’s router micro-architecture are embedded in FPGA hard blocks. Our experimental results show that the topologies implemented employing the proposed FPGA friendly mapping of the NoC router components on the hard blocks consume 43.47% fewer LUTs and 41.66% fewer FFs than the topologies with CLB implementation. To optimize the latency of the NoC under consideration, a control unit called “buf_empty_checker” has been employed. A reduction in average latency has been observed compared to the CLB based topology implementation employing the proposed mapping. The proposed work consumes 10.88% fewer LUTs than the CONNECT NoC generation tool. Compared to DART, a reduction of 73.38% and 66.55% in LUTs and FFs has been observed with respect to the proposed work. The average packet latency of the proposed NoC architecture is 24.8% and 19.1% lesser than the CONNECT and DART architectures.