Abstract
Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.
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References
Acha JI (1989) Computational structures for fast implementation of L-path and L-block digital filters. IEEE Trans Circuits Syst 36(6):805–812
Antoniou A (1993) Digital filter: analysis, design and applications. McGraw-Hill, New York
Chandra A, Chattopadhyay S (2015) Design of hardware efficient FIR filter: a review of the state of the art approaches. Int J 19:212–226
Chung JG, Parhi KK (2002) Frequency-spectrum-based low-area low-power parallel FIR filter design. EURASIP J Appl Signal Process 2002(9):444–453
Gupta T, Sharma JB (2018) Han-Carlson adder based high-speed vedic multiplier for complex multiplication. Microsyst Technol 24:3901–3906 (ISSN 0946-7076)
Han T, Carlson D (1987) Fast area-efficient VLSI Adders. In: Proceedings of 8th Symposium on Computer Arithmetic, pp 49–56
Kerur SS, Narchi JCP, Kittur HM, Girish VA (2011) Implementation of vedic multiplier for digital signal processing. Int J Comput Appl 16:1–5
Meher PK, Park SY (2011) High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic. In: Proceedings of IEEE/IFIP19th International Conference on VLSI-SOC, pp 428–433
Mitra SK (2001) Digital signal processing: a computer-based approach, 2nd edn. McGraw Hill, New York
Mitttal A, Nandi A, Yadav D (2017) Comparative study of 16-order FIR filter design using different multiplication techniques. IET Circuits Devices Syst 11(3):196–200
Mohanty BK, Meher PK (1988) Novel flexible systolic mesh architecture for parallel VLSI implementation of finite digital convolution. IETE J Res 44(6):261–266
Moni DJ, Sophia PE (2011) Design of low power and high speed configurable booth multiplier. In: Proceedings of IEEE, 978-1-4244-8679-3/11
Mou Z-J, Duhamel P (1987) Fast FIR filtering: algorithms and implementations. Signal Process 13:377–384
Mou ZJ, Duhamel P (1991) Short-length FIR filters and their use in the fast non-recursive filtering. IEEE Trans Signal Process 39(6):1322–1332
Paliwal P, Sharma JB (2018a) Fast FIR algorithm based symmetric FIR filter using Han-Carlson adder and vedic multiplier. Int J Pure Appl Math 118(24):1–13
Paliwal P, Sharma JB (2018b) Efficient FPGA implementation architecture of fast FIR algorithm using Han-Carlson adder based Vedic multiplier. In: Proceedings of the international conference on inventive research in computing applications (ICIRCA 2018), pp 643–646
Parker DA, Parhi KK (1996) Area-efficient parallel FIR digital filter implementations. In: International conference on application-specific systems, architectures and processors, Chicago, IL
Parker DA, Parhi KK (1997) Low-area/power parallel FIR digital filter implementations. J VLSI Signal Process Syst 17(1):75–92
Pearson DN, Parhi KK (1995) Low-power FIR digital filter architectures. In: Proceedings of IEEE International Symposium on circuits and systems, Seattle, WA, pp 231–234
Proakis JG (2008) Digital signal processing: principles, algorithms and applications, 4th edn. New Delhi, Prentice Hall of India
Ramkumar B, Kittur HM (2012) Low-power and area-efficient carry select adder. IEEE Trans VLSI Syst 20(2):371–375
Tsao T-C, Choi K (2012) Area-efficient parallel fir digital filter structures for symmetric convolutions based on fast FIR algorithm. IEEE Trans VLSI Syst 20(2):366–371
Uma R, Vijayan V, Mohanapriya M, Paul S (2012) Area, delay and power comparison of adder topologies. Int J VLSI Des Commun Syst 3(1):153
Zergainoh A, Duhamel P (1995) Implementation and performance of composite fast FIR filtering algorithms. In: IEEE signal processing society workshop on VLSI signal processing, Sakai, Japan, pp 267–276
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Paliwal, P., Sharma, J.B. & Nath, V. Comparative study of FFA architectures using different multiplier and adder topologies. Microsyst Technol 26, 1455–1462 (2020). https://doi.org/10.1007/s00542-019-04678-8
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DOI: https://doi.org/10.1007/s00542-019-04678-8