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Design of resistive random access memory cell and its architecture

  • Shashank Kumar Dubey
  • Aminul IslamEmail author
Technical Paper
  • 28 Downloads

Abstract

This paper provides an insight into an alternative technology which makes use of new circuit element called memristor which can be scaled down to advanced technology generation. Power gating technique cannot be used on generally used volatile memories to reduce power dissipation. To overcome this problem nonvolatile memories are required. The nonvolatile memory bitcell used in this article is suitable candidate to replace the generally used memory bitcell like volatile 6T-SRAM bitcell. This article proposes 2T1M (two transistor and one memristor)-based bitcell for data storage. Its operations such as read and write are discussed and the results obtained during various simulations are thoroughly explained. 2T1M-based RRAM bitcell is designed along with write driver and read circuitry. Read time and write time of the proposed RRAM cell are observed by varying supply voltage. An 8 × 8 RRAM architecture based on the proposed bitcell has been also designed. All the simulations are done on the SPICE to show the robustness of proposed 2T1M-based bitcell.

Notes

References

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Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of ECEBIT, MesraRanchiIndia

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