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An efficient circuit-level power reduction technique for ultralow power applications

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Abstract

This research work explores various circuit-level design techniques to identify the best technique suitable for low power circuit design. To establish a proper performance comparison, reported techniques are implemented in a transmission gate-based carry skip adder circuit @ 22-nm technology node. Results obtained demonstrate that the multi-threshold CMOS technique offers the best performance under the given conditions. Further, a novel modified hybrid circuit design technique is also proposed in this paper. To validate the proposed design technique, performance metrics of the carry-skip adder circuit implemented using the proposed hybrid technique and other low power circuit design techniques are compared. Obtained results establish that the proposed technique offers improvement in terms of propagation delay (TP), average power dissipation (PAVG), power delay product (PDP) and leakage power (LP), when compared with its counterpart at a supply voltage of 0.4 V.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India

    Manisha Guduri, Amit Krishna Dwivedi, Sananya Majumder,  Riya & Aminul Islam

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  1. Manisha Guduri
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  2. Amit Krishna Dwivedi
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  3. Sananya Majumder
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  4. Riya
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  5. Aminul Islam
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Correspondence to Aminul Islam.

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Guduri, M., Dwivedi, A.K., Majumder, S. et al. An efficient circuit-level power reduction technique for ultralow power applications. Microsyst Technol 25, 1689–1697 (2019). https://doi.org/10.1007/s00542-018-4103-z

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