Comparative study on drain current conduction mechanisms of (100)- and (111)-silicon nanowire using a quantitative current model
Over the years, semiconductor nanowires have been extensively researched due to their electrical properties for implementation of nano-to-microscale field-effect transistors (FETs). In order to implement a nanowire integrated device, well-aligned arrays of silicon nanowire are necessary for scalable and repeatable mass production. Although there has been much research on various fabrication processes to implement arrayed silicon-nanowires, few studies on channel conduction mechanism and theoretical modeling have been conducted on top-down fabricated silicon nanowires. In this paper, a comparative study on electrical characteristics of (100)- and (111)-silicon nanowire using a quantitative current model is presented for high-performance silicon-nanowire devices. Compared to silicon nanowire using (100)-silicon, one of the advantages of using (111)-silicon is that it can control the height and width of silicon nanowire through a sequential deep-silicon-etching process. According to the operation mechanism of the silicon-nanowire FET, the height of the silicon nanowire needs to be minimized to achieve high on/off-current ratio and low power consumption at off-state. Using (111)-silicon, it is possible to define height and width independently, which can result in higher performance characteristics.
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP; Ministry of Science, ICT & Future Planning) (No. NRF-2017R1C1B5017561).
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