Effective resistance calculation and automated solution for fixing reliability verification violations
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This paper covers the automation done to upgrade the reliability verification in the backend circuit design of microchips. Automation is done to upgrade the reduction of violations which occurs during the reliability verification flow by considering each branch or loop resistors and calculating the current through each resistor. It is also estimated that number of straps required particularly for via 3 and via 4 violations so that to reduce number of RV flow execution. Automation is extremely basic in enhancing the proficiency of plan and assembling phases of a VLSI product. This paper gives a flow, which enhances the efficiency of effective resistance thereby improves the proficiency of reliability verification. This reliability verification (RV) analysis flow, can be invoked post Routing of the plan and encourages the VLSI designers to recognize the adjustments in current design, that caused the signal scaling factors (SF)/self-heat violations from past one. This automation essentially decreases SF/self-heat in the circuit by reducing the resistance, in this way decreasing the back end configuration time.
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