Abstract
The paper discusses a unique method to design low power circuits, which is called Gate Diffusion Input (GDI) method. Complex functions can be implemented using only two transistors by using this method. GDI technique allows for reduced power consumption, lower delay, lesser transistor count and decreased area of circuits. It also makes the system design less complex. Full adders and parallel adders, are major building blocks of different digital components like ALUs, DSPs etc. Hence, reducing power consumption of adders is very important. This work aims at building a parallel adder that consumes less power. A GDI based XOR gate is designed using which, a 10T full adder is designed which involves lesser number of devices compared to CMOS Full adder. The threshold loss in full adder is a major pitfall. A standard CMOS process compatible version of GDI cell, modified GDI, mGDI cell is proposed, using which a full adder is built. A 4-bit parallel adder is designed. The proposed technique consumes lesser area and has low power dissipation compared to CMOS design. Power consumption is reduced by 15% compared to CMOS design. Cadence tool at 180 nm is used to implement the designs.
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References
Bui HT, Wang Y, Jiang Y (2002) Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates. Proc IEEE Trans Circuits Syst II 49:25–30
Calhoun B, Cao Y, Li X, Mai K, Pileggi L, Rutenbar R, Shepard K (2008) Digital circuit design: challenges and opportunities in the era of nanoscale CMOS. Proc IEEE 96(2):343–365
Fish A, Morgenshtein A, Wagner IA (2002) Gate-diffusion input (GDI)-a technique for low power design circuits: analysis and characterization. Proc IEEE Int Symp Circuits Syst 1:477–480
Fish A, Morgenshtein A, Shwartz I (2010) Gate diffusion input (GDI) logic in standard CMOS nanoscale process. In Proceedings of IEEE 26th Convention of Electrical and Electronics Engineers in Israel 776–780
Nazarian S, Pedram M (2006) Thermal modeling, management and analysis in VLSI circuits: principles and methods. Proc IEEE 94(8):1487–1501
Ram S, Ahamed RR (2013) Comparison and analysis of combinational circuits using different logic styles. In Proceedings of Fourth International Conference on Computing, Communication and Networking Technologies (ICCCNT), 1–6
Ravish Aradhya HV, Madan HR (2014) Design and optimization of reversible carry look ahead adder. Proc Int J Electron Commun Eng Res 3(3):65–72
Ravish Aradhya HV, Pattar SM (2013) Novel low power 8T full adder. Proc Int J Sci Eng Res 4(8):1156–1160
Ravish Aradhya HV, Lakshmeesha J, Muralidhara KN (2013) Reduced complexity hybrid ripple carry look ahead adder. Proc Int J Comput Archit IJCA 70(28):13–16
Shams AM, Zhang GM (2005) A review of 0.18 μm full adder performances for tree structure arithmetic circuits. Proc IEEE Trans Very Large Scale Integr (VLSI) Syst 13:686–695
Shrivas J, Akashe S, Tiwari N (2012) Design and performance analysis of 1 bit full adder using GDI technique in nanometer era. In the Proceedings of IEEE World Congress on Information and Communication Technologies (WICT), 822–825
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Smitha, G.S., Ravish Aradhya, H.V. mGDI based parallel adder for low power applications. Microsyst Technol 25, 1653–1658 (2019). https://doi.org/10.1007/s00542-017-3438-1
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DOI: https://doi.org/10.1007/s00542-017-3438-1