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Impact of polyimide liner on high-aspect-ratio through-silicon-vias (TSVs): electrical characteristics and copper protrusion

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Abstract

Through silicon vias (TSVs) are key components in three dimensional integrated circuits. The performance of TSVs insulation layer strongly affects electrical characteristics and thermal mechanical reliability of TSVs. This paper reports impact of polyimide liner as TSVs sidewall insulation on electrical characteristics and copper protrusion of high-aspect-ratio TSVs. The strategy of polyimide liner based via-last 3D integration are described in detail for future application. Electrical characteristics including leakage current and capacitance–voltage characteristics indicate excellent insulation ability (~10−12 A at 20 V) of polyimide liner and low parasitic capacitance density (~10−9 F/cm2) of the TSVs. The impact of polyimide liner on copper protrusion (~668 nm at 350 °C) is investigated under various annealing temperatures. The results show protrusion height increases with annealing temperature.

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Acknowledgements

This work was supported in part by the National Natural Science Foundation of China under Grant 61404008 and 61574016 and in part by 111 Project of China under Grant B14010.

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Authors and Affiliations

  1. School of Information and Electronics, Beijing Institute of Technology, Beijing, 100081, China

    Shiwei Wang, Yangyang Yan, Zhiqiang Cheng, Zhiming Chen & Yingtao Ding

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  1. Shiwei Wang
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  2. Yangyang Yan
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  3. Zhiqiang Cheng
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  4. Zhiming Chen
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  5. Yingtao Ding
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Correspondence to Zhiming Chen.

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Wang, S., Yan, Y., Cheng, Z. et al. Impact of polyimide liner on high-aspect-ratio through-silicon-vias (TSVs): electrical characteristics and copper protrusion. Microsyst Technol 23, 3757–3764 (2017). https://doi.org/10.1007/s00542-016-3243-2

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  • DOI: https://doi.org/10.1007/s00542-016-3243-2

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