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Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications

Abstract

In this work, the effect of gate metal work function engineering (GME), gate bias and drain bias on the bias dependent parasitic capacitances has been studied. Further, RF Figure of merits (FOMs) such as power gains, cut-off frequency (f T), maximum oscillation frequency (f Max) and intrinsic delay of hetero-dielectric gate-metal-engineered gate-all-around tunnel FET (HD-GME-GAA-TFET) are studied and compared with HD-GAA-TFET. Simulation results show an appreciable improvement in RF FOMs with the application of GME architecture on GAA TFET. Further, it has been observed that GME exhibits 3.76 times enhancement and 0.017 times reduction in cut-off frequency and intrinsic delay respectively as we increase the work function difference, which makes it a promising candidate for low power switching applications. Moreover, the small signal Y-parameters have also been studied which indicates that HD-GME-GAA-TFET is a promising candidate for RF/microwave applications. All the simulations have been done using ATLAS device simulator.

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Acknowledgments

Authors would like to thank to Microelectronics Research Lab, Department of Engineering Physics Delhi Technological University to carry out this work. One of the authors (Jaya Madan) would like to thank University Grants Commission, Govt. of India, for providing the necessary financial assistance during the course of this research work.

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Correspondence to Rishu Chaujar.

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Madan, J., Gupta, R.S. & Chaujar, R. Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications. Microsyst Technol 23, 4081–4090 (2017). https://doi.org/10.1007/s00542-016-3143-5

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  • DOI: https://doi.org/10.1007/s00542-016-3143-5

Keywords

  • Parasitic Capacitance
  • Gate Bias
  • Subthreshold Swing
  • Drain Bias
  • Drain Side