Abstract
In this work, the effect of gate metal work function engineering (GME), gate bias and drain bias on the bias dependent parasitic capacitances has been studied. Further, RF Figure of merits (FOMs) such as power gains, cut-off frequency (f T), maximum oscillation frequency (f Max) and intrinsic delay of hetero-dielectric gate-metal-engineered gate-all-around tunnel FET (HD-GME-GAA-TFET) are studied and compared with HD-GAA-TFET. Simulation results show an appreciable improvement in RF FOMs with the application of GME architecture on GAA TFET. Further, it has been observed that GME exhibits 3.76 times enhancement and 0.017 times reduction in cut-off frequency and intrinsic delay respectively as we increase the work function difference, which makes it a promising candidate for low power switching applications. Moreover, the small signal Y-parameters have also been studied which indicates that HD-GME-GAA-TFET is a promising candidate for RF/microwave applications. All the simulations have been done using ATLAS device simulator.
Similar content being viewed by others
References
Anghel C, Chilagani P, Amara A, Vladimirescu A (2010) Tunnel field effect transistor with increased on current, low-k spacer and high-k dielectric. Appl Phys Lett 96:122104. doi:10.1063/1.3367880
ATLAS user’s manual (2014) Silvaco Int, Santa Clara
Bhuwalka KK, Schulze J, Eisele I (2004) Performance enhancement of vertical tunnel field-effect transistor with SiGe in the δp+ layer. Jpn J Appl Phys 43:4073–4078. doi:10.1143/JJAP.43.4073
Brouzet V, Salem B, Periwal P, Rosaz G, Baron T, Bassani F, Gentile P, Ghibaudo G (2015) Fabrication and characterization of silicon nanowire p-i-n MOS gated diode for use as p-type tunnel FET. Appl Phys A 121(3):1285–1290. doi:10.1007/s00339-015-9507-3
Chattopadhyay A, Mallik A (2011) Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor. IEEE Trans Electron devices 58(3):677–683. doi:10.1109/TED.2010.2101603
Chen ZX, Yu HY, Singh N, Shen NS, Sayanthan RD, Lo GQ, Kwong DL (2009) Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires. IEEE Electron Device Lett 30(7):754–756. doi:10.1109/LED.2009.2021079
Choi WY, Lee W (2010) Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans Electron Devices 57(9):2317–2319. doi:10.1109/TED.2010.2052167
Gandhi R, Chen Z, Singh N, Banerjee K, Lee S (2011a) CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with ≤50-mV/decade subthreshold swing. IEEE Electron Device Lett 32(11):1504–1506. doi:10.1109/LED.2011.2165331
Gandhi R, Chen Z, Singh N, Banerjee K, Lee S (2011b) Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤50 mV/decade) at room temperature. IEEE Electron Device Lett 32(4):437–439. doi:10.1109/LED.2011.2106757
Ghosh B, Akram MW (2013) Junctionless tunnel field effect transistor. IEEE Electron Device Lett 34(5):584–586. doi:10.1109/LED.2013.2253752
Guo P, Yang Y, Cheng Y, Han G, Pan J, Zhang Z, Hu H, Shen ZX, Chia CK, Yeo YC (2013) Tunneling field-effect transistor with Ge/In0.53Ga 0.47As heterostructure as tunneling junction. J Appl Phys 113:094502. doi:10.1063/1.4794010
Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479:329–337. doi:10.1038/nature10679
Kavalieros J, Doyle B, Datta S, Dewey G, Doczy M, Jin B, Lionberger D, Metz M, Rachmady W, Radosavljevic M, Shah U, Zelick N, Chau R (2006) Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering. Symposium on VLSI Technology Digest of Technical Papers, pp 5–6. doi: 10.1109/VLSIT.2006.1705211
Kim SH, Kam H, Hu C, Liu TJK (2009) Germanium-source tunnel field effect transistors with record high ION/IOFF. Symposium on VLSI Technology Digest of Technical papers, pp 178–179
Lee JS, Choi WY, Kang IM (2012) Characteristics of gate all around hetero gate dielectric tunneling field effect transistor. Jpn J Appl Phys 51:06FE03. doi:10.1143/JJAP.51.06FE03
Lee JS, Seo JH, Cho S, Lee JH, Kang SW, Bae JH, Cho ES, Kang IM (2013) Simulation study on effect of drain underlap in gate-all around tunneling field-effect transistors. Curr Appl Phys 13(6):1143–1149. doi:10.1016/j.cap.2013.03.012
Long W, Ou H, Kuo JM, Chin KK (1999) Dual-material gate (DMG) field effect transistor. IEEE Trans Electron Devices 46(5):865–870. doi:10.1109/16.760391
Madan J, Chaujar R (2016) Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans Device Mater Reliab 16(2):227–234. doi:10.1109/TDMR.2016.2564448
Madan J, Gupta RS, Chaujar R (2015a) Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor. Jpn J Appl Phys 54:094202. doi:10.7567/JJAP.54.094202
Madan J, Gupta RS, Chaujar R (2015b) TCAD analysis of small signal parameters and RF performance of heterogeneous gate dielectric-Gate all around Tunnel FET. Adv Manuf Electron Microsyst Techconnect Briefs 2015:189–192
Madan J, Gupta RS, Chaujar R (2016) Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications. Microsyst Technol. doi:10.1007/s00542-016-2872-9
Polishchuk I, Ranade P, King TJ, Hu C (2001) Dual work function metal gate CMOS technology using metal interdiffusion. IEEE Electron Device Lett 22(9):444–446. doi:10.1109/55.944334
Razavi B (1998) RF microelectronics. Prentice Hall, Upper Saddle River, p 2
Saurabh S, Kumar MJ (2011) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electron Devices 58(2):404–410. doi:10.1109/TED.2010.2093142
Toh EH, Wang GH, Samudra G, Yeo YC (2008) Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications. J Appl Phys 103:104504. doi:10.1063/1.2924413
Vallett AL, Minassian S, Kaszuba P, Datta S, Redwing JM, Mayer TS (2010) Fabrication and characterization of axially doped silicon nanowire tunnel field-effect transistors. Nano Lett 10(12):4813–4818. doi:10.1021/nl102239q
Vandooren A, Leonelli D, Rooyackers R, Hikavyy A, Devriendt K, Demand M, Loo R, Groeseneken G, Huyghebaert C (2013) Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs. Solid State Electron 83:50–55. doi:10.1016/j.sse.2013.01.026
Verhulst AS, Vandenberghe WG, Maex K, Groeseneken G (2007) Tunnel field-effect transistor without gate-drain overlap. Appl Phys Lett 91:053102. doi:10.1063/1.2757593
Wang PF, Hilsenbeck K, Nirschl T, Oswald M, Stepper C, Weis M, Schmitt-Landsiedel D, Hansch W (2004) Complementary tunneling transistor for low power application. Solid State Electron 48(12):2281–2286. doi:10.1016/j.sse.2004.04.006
Wang X, Ouyang Y, Li X, Wang H, Guo J, Dai H (2008) Room-temperature all-semiconducting sub-10-nm graphene nanoribbon field-effect transistors. Phys Rev Lett 100(20):100–103. doi:10.1103/PhysRevLett.100.206803
Wu YQ, Xu M, Wang RS, Koybasi O, Ye PD (2009) High performance deep-submicron inversion-mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/μm: new HBr pretreatment and channel engineering. IEEE International Electron Devices Meeting (IEDM), pp 1–4. doi: 10.1109/IEDM.2009.5424358
Yang Y, Tong X, Yang LT, Guo PF, Fan L, Yeo YC (2010) Tunneling field-effect transistor: capacitance components and modeling. IEEE Electron Device Lett 31(7):752–754. doi:10.1109/LED.2010.2047240
Yang Y, Han G, Guo P, Wang W, Gong X, Wang L, Low KL, Yeo YC (2013) Germanium-Tin P-channel tunneling field-effect transistor : device design and technology demonstration. IEEE Trans Electron Devices 60(12):4048–4056. doi:10.1109/TED.2013.2287031
Zhang L, Lin X, He J, Chan M (2012) An analytical charge model for double-gate tunnel FETs. IEEE Trans Electron Devices 59(12):3217–3223. doi:10.1109/TED.2012.2217145
Acknowledgments
Authors would like to thank to Microelectronics Research Lab, Department of Engineering Physics Delhi Technological University to carry out this work. One of the authors (Jaya Madan) would like to thank University Grants Commission, Govt. of India, for providing the necessary financial assistance during the course of this research work.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Madan, J., Gupta, R.S. & Chaujar, R. Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications. Microsyst Technol 23, 4081–4090 (2017). https://doi.org/10.1007/s00542-016-3143-5
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00542-016-3143-5