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Design of a power efficient, high slew rate and gain boosted improved recycling folded cascode amplifier with adaptive biasing technique

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Abstract

This paper presents an adaptive Improved Recycling Folded Cascode (IRFC) amplifier with improved gain, high slew rate, high phase margin and reduced power consumption. The proposed design is implemented using 180 nm technology with a supply voltage of 1.8 V and a capacitive load of 1 pF. The proposed design is compared with basic two stage op-amp, cascode amplifier and conventional recycling folded cascode amplifier (RFC). Analysis demonstrates that the flexible structure of IRFC with adaptive biasing shows an improvement in gain to 87.74 dB, approximately three times enhancement in slew rate to 53.8 V/µs when compared with the design specifications. The phase margin was observed to be 64.86°. The design also reports an increase in output swing. The gain increases to 109 dB when a cascode stage is added to the IRFC structure.

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Authors and Affiliations

  1. School of Electronics Engineering, KIIT University, Bhubaneswar, 751024, India

    Arnab Sarkar & Soumya Shatakshi Panda

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  1. Arnab Sarkar
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  2. Soumya Shatakshi Panda
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Correspondence to Soumya Shatakshi Panda.

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Sarkar, A., Panda, S.S. Design of a power efficient, high slew rate and gain boosted improved recycling folded cascode amplifier with adaptive biasing technique. Microsyst Technol 23, 4255–4262 (2017). https://doi.org/10.1007/s00542-016-2969-1

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  • DOI: https://doi.org/10.1007/s00542-016-2969-1

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