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Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications

Abstract

This paper presents a mathematical modeling insight for the novel heterogate dielectric-dual material gate-GAA TFET (HD-DMG-GAA-TFET) and validating the results with TCAD simulation. By using the appropriate boundary conditions and continuity equations, the Poisson’s equation is solved to obtain the potential profile. The developed model is used to study the analog performance parameters such as subthreshold swing (SS), threshold voltage (Vth), transconductance (gm), drain conductance (gd), device efficiency (gm/Ids), intrinsic gain (gm/gd), channel resistance (Rch) and output resistance (Ro). Further, to optimize the effect of metal work function on analog performance, three different combinations of DMG configurations has been studied. The results demonstrated that for a difference of 0.4 eV, the analog performance of the device is optimized. Low off current and high value of on current resulting into a higher ION/IOFF ratio has been obtained, which is appropriate for sub-nanometre devices and low standby power applications. The analytical results obtained from the proposed model shows good agreement with the simulated results obtained with the ATLAS device simulator.

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Acknowledgments

Authors would like to thank Microelectronics Research Lab, Department of Engineering Physics Delhi Technological University to carry out this work. One of the authors (Jaya Madan) would like to thank University Grants Commission, Govt. of India, for providing the necessary financial assistance during the course of this research work.

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Correspondence to Rishu Chaujar.

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Madan, J., Gupta, R.S. & Chaujar, R. Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications. Microsyst Technol 23, 4091–4098 (2017). https://doi.org/10.1007/s00542-016-2872-9

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  • DOI: https://doi.org/10.1007/s00542-016-2872-9

Keywords

  • Analog Performance
  • Tunneling Junction
  • Drain Current
  • Gate Bias
  • Output Resistance