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Wafer level high-density trench capacitors by using a two-step trench-filling process

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Abstract

This paper reports on the design, fabrication and electrical characterization of high-density SIS trench capacitors by using a two-step deposition process for fast-filling the deep trenches. LPCVD silicon nitride is employed as the dielectric material to provide high efficiency deposition in the high aspect ratio trenches. The capacitance density in trench capacitors with 25 nm thick Si3N4 is characterized as high as 57.8 nF/mm2, while the breakdown voltage in trench capacitors with 35 nm thick Si3N4 is recorded to be as high as 14.5 V. Furthermore, the capacitances are measured over an applied voltage range from −5 to 5 V, showing a small voltage-dependence of 1.2 and 0.6 % V−1 for the 25 and 35 nm thick Si3N4 trench capacitor, respectively. The leakage currents are measured and the current transport mechanisms are analyzed. The ESR and ESL of the capacitors with 25 and 35 nm thick Si3N4 are very small, as low as 35–65 mΩ and 0.2–0.28 pH for 0.04 mm2 electrode surface.

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Acknowledgments

The authors would like to thank SIMIT for the manufactory platform and package implementation.

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Correspondence to Le Luo.

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Zheng, T., Xu, G. & Luo, L. Wafer level high-density trench capacitors by using a two-step trench-filling process. Microsyst Technol 23, 399–404 (2017). https://doi.org/10.1007/s00542-015-2681-6

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  • DOI: https://doi.org/10.1007/s00542-015-2681-6

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